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SRIO Functional Description
Figure 30. DMA Example
DMA Example |
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to |
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from |
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| fset | This |
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involves |
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response |
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| RapidIO |
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| 0 |
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| RapidIO |
| MMR | fset |
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| A0 | A1 | A2 |
| A3 |
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| MMR | fset |
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| B0 | B1 | B2 |
| B3 |
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| MMR |
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| MMR | fset |
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| C0 | C1 | C2 | C3 |
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| MMR | fset |
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| D0 | D1 | D2 | D3 |
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| Header |
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| A0A1A2A3B0B1B2B3 |
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| Response |
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Big |
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| Little | ||
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| Byte |
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| Byte |
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| Byte | ||||||
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| lane |
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| lane |
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| lane |
| lane | ||||||||
L2 | fset |
| A0 |
| A1 |
| A2 |
| A3 |
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| L2 |
| fset |
| A3 | A2 | A1 | A0 |
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L2 | fset |
| B0 |
| B1 |
| B2 |
| B3 |
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| L2 |
| fset |
| B3 | B2 | B1 | B0 |
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L2 | fset |
| C0 | C1 | C2 | C3 |
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| L2 |
| fset |
| C3 | C2 | C1 | C0 |
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L2 | fset |
| D0 | D1 | D2 | D3 |
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| L2 | fset |
| D3 | D2 | D1 | D0 |
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2.3.9Reset
The RapidIO peripheral allows independent software controlled shutdown for the following blocks: SERDES TX and RX individual ports and PLL, channelized datapath logic (8b/10b, rate handoff FIFO, CRC logic, lane
Reset of the SERDES macros is handled independently of the registers discussed in this section. The SERDES can be configured to shutdown unused links or fully shutdown. SERDES TX and RX channels may be enabled/disabled by writing to bit 0 of the SERDES_CFGTXn_CNTL and SERDES_CFGRXn_CNTL registers. The PLL and remaining SERDES functional blocks can be controlled by writing to the ENPLL signals in the PER_SET_CNTL or SERDES_CFGn_CNTL register, depending on device implementation. These registers will drive the SERDES signal inputs, which will gate the reference clock to these blocks internally. This reference clock is sourced from a device pin specifically for the SERDES and is not derived from the CPU clock, thus it resets asynchronously. ENPLL will disable all SERDES
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64 | Serial RapidIO (SRIO) | SPRU976 |