DMA Example, Reset | Texas Instruments TMS320C645x guide

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SRIO Functional Description

Figure 30. DMA Example

DMA Example

The

Type

The

from

fset

This

involves

for

response

RapidIO

MMR

fset

MMR

fset

defined

MMR

fset

offsets

MMR

fset

Type

Header

A0A1A2A3B0B1B2B3

Response

Double-word0

Double-word1

Big

Little

Byte

lane

fset

2.3.9Reset

The RapidIO peripheral allows independent software controlled shutdown for the following blocks: SERDES TX and RX individual ports and PLL, channelized datapath logic (8b/10b, rate handoff FIFO, CRC logic, lane striping/de-skew logic), CPPI module, LSU module, MAU module, and MMR registers. With the exception of BLK_EN0 for the MMR registers, when the BLKn_EN signals are deasserted, the clocks are gated to these blocks, effectively providing a shutdown function.

Reset of the SERDES macros is handled independently of the registers discussed in this section. The SERDES can be configured to shutdown unused links or fully shutdown. SERDES TX and RX channels may be enabled/disabled by writing to bit 0 of the SERDES_CFGTXn_CNTL and SERDES_CFGRXn_CNTL registers. The PLL and remaining SERDES functional blocks can be controlled by writing to the ENPLL signals in the PER_SET_CNTL or SERDES_CFGn_CNTL register, depending on device implementation. These registers will drive the SERDES signal inputs, which will gate the reference clock to these blocks internally. This reference clock is sourced from a device pin specifically for the SERDES and is not derived from the CPU clock, thus it resets asynchronously. ENPLL will disable all SERDES high-speed output clocks. Since these clocks are distributed to all the links, ENPLL should only be used to completely shutdown the peripheral. It should be noted that shutdown of SERDES links in between normal packet transmissions is not permissible for two reasons. First, the serial RapidIO sends idle packets between data packets to maintain synchronization and lane alignment. Without this mechanism, the RapidIO RX logic can be mis-aligned for both 1X and 4X ports. Second, the lock time of the SERDES PLL would need to reoccur, which would slow down the operation.

All chip-IO signals must be reset asynchronously to a known state. When the SERDES ENTX signal is held low, the corresponding transmitter is powered down. In this state, both outputs, TXP and TXN, will be pulled high to VDDT.

Serial RapidIO (SRIO)

SPRU976 –March 2006

Texas Instruments TMS320C645x manual DMA Example, Reset

Models: TMS320C645x

Figure 30. DMA Example

2.3.9Reset

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