| 5.25 | Error, Reset, and Special Event Clear Interrupt Register (ERR_RST_EVNT_ICCR) | 126 |
| 5.26 | DOORBELLn Interrupt Condition Routing Register (DOORBELLn_ICRR) | 127 |
| 5.27 | DOORBELLn Interrupt Condition Routing Register 2 (DOORBELLn_ICRR2) | 128 |
| 5.28 | RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR) | 129 |
| 5.29 | RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR2) | 130 |
| 5.30 | TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR) | 131 |
| 5.31 | TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR2) | 132 |
| 5.32 | LSU Module Interrupt Condition Routing Register 0 (LSU_ICRR0) | 133 |
| 5.33 | LSU Module Interrupt Condition Routing Register 1 (LSU_ICRR1) | 134 |
| 5.34 | LSU Module Interrupt Condition Routing Register 2 (LSU_ICRR2) | 135 |
| 5.35 | LSU Module Interrupt Condition Routing Register 3 (LSU_ICRR3) | 136 |
| 5.36 | Error, Reset, and Special Event Interrupt Condition Routing Register |
|
|
| (ERR_RST_EVNT_ICRR) | 137 |
| 5.37 | Error, Reset, and Special Event Interrupt Condition Routing Register 2 |
|
|
| (ERR_RST_EVNT_ICRR2) | 138 |
| 5.38 | Error, Reset, and Special Event Interrupt Condition Routing Register 3 |
|
|
| (ERR_RST_EVNT_ICRR3) | 139 |
| 5.39 | INTDSTn Interrupt Status Decode Registers (INTDSTn_DECODE) | 140 |
| 5.40 | INTDSTn Interrupt Rate Control Registers (INTDSTn_RATE_CNTL) | 141 |
| 5.41 | LSUn Control Register 0 (LSUn_REG0) | 142 |
| 5.42 | LSUn Control Register 1 (LSUn_REG1) | 143 |
| 5.43 | LSUn Control Register 2 (LSUn_REG2) | 144 |
| 5.44 | LSUn Control Register 3 (LSUn_REG3) | 145 |
| 5.45 | LSUn Control Register 4 (LSUn_REG4) | 146 |
| 5.46 | LSUn Control Register 5 (LSUn_REG5) | 147 |
| 5.47 | LSUn Control Register 6 (LSUn_REG6) | 148 |
| 5.48 | LSU Congestion Control Flow Mask n (LSU_FLOW_MASKS n) | 149 |
| 5.49 | Queue Transmit DMA Head Descriptor Pointer Registers (QUEUEn_TXDMA_HDP) | 150 |
| 5.50 | Queue Transmit DMA Completion Pointer Registers (QUEUEn_TXDMA_CP) | 151 |
| 5.51 | Queue Receive DMA Head Descriptor Pointer Registers (QUEUEn_RXDMA_HDP) | 152 |
| 5.52 | Queue Receive DMA Completion Pointer Registers (QUEUEn_RXDMA_CP) | 153 |
| 5.53 | Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) | 154 |
| 5.54 | Transmit CPPI Supported Flow Mask Registers n (TX_CPPI_FLOW_MASKSn) | 155 |
| 5.55 | Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) | 157 |
| 5.56 | Receive CPPI Control Register (RX_CPPI_CNTL) | 158 |
| 5.57 | Transmit CPPI Weighted Round Robin Control Register 0 (TX_QUEUE_CNTL0) | 159 |
| 5.58 | Transmit CPPI Weighted Round Robin Control Register 1 (TX_QUEUE_CNTL1) | 160 |
| 5.59 | Transmit CPPI Weighted Round Robin Control Register 2 (TX_QUEUE_CNTL2) | 161 |
| 5.60 | Transmit CPPI Weighted Round Robin Control Register 3 (TX_QUEUE_CNTL3) | 162 |
| 5.61 | 163 | |
| 5.62 | 164 | |
| 5.63 | Flow Control Table Entry Registers (FLOW_CNTLn) | 165 |
| 5.64 | Device Identity CAR (DEV_ID) | 166 |
| 5.65 | Device Information CAR (DEV_INFO) | 167 |
| 5.66 | Assembly Identity CAR (ASBLY_ID) | 168 |
| 5.67 | Assembly Information CAR (ASBLY_INFO) | 169 |
| 5.68 | Processing Element Features CAR (PE_FEAT) | 170 |
| 5.69 | Source Operations CAR (SRC_OP) | 171 |
| 5.70 | Destination Operations CAR (DEST_OP) | 172 |
| 5.71 | Processing Element Logical Layer Control CSR (PE_LL_CTL) | 173 |
4 | Contents | SPRU976 | |
