Register Descriptions Chapter 4
GPIB-1014 User Manual 4-58 © National Instruments Corporation
Channel Status RegisterVMEbus Address: Base Address + 00 (hex)
Attributes: Read/Write, Internal to DMAC
7 654 321 0
COC BTC NDT ERR ACT 0 PCT PCS R/W
The Channel Status Register (CSR) bits are set automatically by DMAC. Bits are cleared by
writing a one (1) to each register bit or by resetting the DMAC.
Bit Mnemonic Description
7r/w COC Channel Operation Complete bit
The Channel Operation Complete bit is set if the DMA transfer has
completed. This bit is set following the termination, whether
successful or not, of any DMA operation. This bit must be cleared to
start another channel operation.
0 = Channel operation incomplete
1 = Channel operation complete
6r/w BTC Block Termination Complete Bit
The Block Termination Complete bit is set when the memory transfer
count is exhausted, the operation is unchained, and the continue bit is
set. This bit must be cleared before another continuation is attempted;
otherwise, an operation timing error is signaled. See The Continue
Mode of Operation in Chapter 6 for more information.
0 = Block transfer incomplete
1 = Block transfer complete
5r/w NDT Normal Device Termination Bit
The Normal Device Termination bit is set when the transfer operation
is terminated by the device. This is not used in the GPIB-1014
application.
0 = No device termination
1 = Device terminated operation normally