Diagnostic and Troubleshooting Test Procedures Chapter 7
GPIB-1014 User Manual 7-4 © National Instruments Corporation
11B AUXMR = 1E set IFC
11B AUXMR = 16 clear IFC
119 ADSR = 80? CIC
115 ISR2 = 9? CO + ADSC
11B AUXMR = 10 go to standby
119 ADSR = C0? CIC + ATN*
8. Test DMA Error.
105 CFG2 = 0A Set LMR and turn LED green
105 CFG2 = 08 Clear LMR
007 CCR0 = 80 start channel 0
007 CCR0 = 10 abort channel 0
000 CSR0 = 91? COC & Error
000 CSR0 = 90 clear bits
000 CSR0 = 01? bits cleared
9. Test DMAC Interrupt Detection.
105 CFG2 = 0A Set LMR and turn LED green
105 CFG2 = 08 Clear LMR
044 DCR1 = 00 PCL Status Input, channel 1
040 CSR1 = FF Clear bits, channel 1
11B AUXMR = 2 TLC Reset
11B AUXMR = A0 Clear INV
119 ADMR = 80 ton
113 IMR1 = 2 DO IE
11B AUXMR = 0 Immediate execute pon
040 CSR1 = 2? PCL transition occurred
113 ISR1 = 2? DO
040 CSR1 = 3? TLC interrupt cleared
040 CSR1 = FF
040 CSR1 = 01? bit reset
10. Test memory-to-memory (flowthrough) DMA transfer.
105 CFG2 = 0A Set LMR and turn LED green
105 CFG2 = 08 Clear LMR
080 CSR2 = FF Reset Channel 2 status register
084 DCR2 = 08 Burst mode, 16-bit transfer with 68000 dev
085 OCR2=11 Mem to dev, word xtfr, no chain, internal req
086 SCR2=05 MAC and DAC both count up
08A MTC2=0005 5 words (10 bytes) transfer
0A9 MFC2=06
0B1 DFC2=06
08C MAR2=daddr 4-byte data address (Ex: 00200000)
094 DAR2=daddr+0A 4-byte data address (Ex: 0020000A)
101 CFG1=00 no interrupt, BR0*&BG0*, no carry cycle, enable
ROR feature