Register Descriptions Chapter 4
GPIB-1014 User Manual 4-46 © National Instruments Corporation
DMA Registers
The onboard DMA Controller is a 68450 DMAC. This chip is extremely flexible and uses four
independent DMA channels. The DMAC can support single address (flyby) transfers or dual
address (flowthrough) transfers. The GPIB-1014 uses two channels (Channel 0 and 1) for 8-bit
flyby DMA transfers between VMEbus memory and the GPIB. All four channels are available
for 8- or 16-bit flowthrough memory-to-memory DMA transfers. The DMAC supports
unchained, continue, array chained, or link chained operations between memory and memory or
between memory and device (GPIB). The TLC-to-DMAC interface includes lines for
requesting, acknowledging, and providing incidental control of the TLC.
The DMAC contains a large number of internal configuration and status registers. These
registers define and control the activity of the DMAC in processing a channel operation. The
registers are addressed relative to the base address of the board. Locations not used in the board
address space are reserved.
The registers set associated with each DMA channel is shown in Table 4-7.
Table 4-7. DMAC DMA Channel Register Set
Register Name Mnemonic Size
Memory Address Register MAR 32 bits
Memory Transfer Counter Register MTCR 16 bits
Memory Function Code Register MFCR 8 bits
Device Address Register DAR 32 bits
Device Function Code Register DFCR 8 bits
Base Address Register BAR 32 bits
Base Transfer Counter Register BTCR 16 bits
Base Function Code Register BFCR 8 bits
Channel Status Register CSR 8 bits
Channel Error Register CER 8 bits
Device Control Register DCR 8 bits
Operation Control Register OCR 8 bits
Sequence Control Register SCR 8 bits
Channel Control Register CCR 8 bits
Channel Priority Register CPR 8 bits
Normal Interrupt Vector Register NIVR 8 bits
Error Interrupt Vector Register EIVR 8 bits
The register set for each channel is addressed relative to the base address of the GPIB-1014 as
outlined in Table 2-2. Figure 4-3 shows the DMA registers in order of their register offset.
Figure 4-3 is reprinted with permission of the copyright owner from the Motorola MC68440
Dual-Channel Direct Memory Access Controller, Advance Information, February 1984 Edition,
p. 3-20. © Copyright 1984 Motorola, Inc.