National Instruments 320030-01

Chapter 5 Programming Considerations

• For array or linked chaining, load the MFCR of Channel 0 with the proper data to

generate the required Address Modifier Code to access the data blocks. See Tables

3-1 and 3-2 for recommended values.

• Set up the data blocks and the address & transfer count array in VMEbus memory.

The total number of bytes in the data block should be n-1 bytes. Figures 6-1 and 6-2

describe how to set up the array for both chaining modes.

h. Finally, interrupts are generally not enabled in Channel 0. The CPR, NIVR, DAR,

DFCR, and EIVR of Channel 0 are generally not used.

3. Channel 1 is used to control the interrupts from the board and to implement the carry cycle

feature. A carry cycle array is constructed in memory. Chaining is used to transfer the array.

The carry cycle array is just an address & transfer count array (that is, an array of pointers

that point to the data blocks to be transferred). The procedure for configuring Channel 1 is as

follows:

a. Write to the CCR of Channel 1 with the SAB bit set to abort the channel operation in case

it is still active.

b. Write 0xFF (hex) to the CSR of Channel 1 to clear any leftover error or status bits.

c. Load the DCR of Channel 1 with the proper value to select the DMA transfer mode, cycle

steal without hold, or cycle steal with hold. Set the DTYP bits to 10 (device with ACK*,

implicitly addressed); set the DPS bit to 0 (8-bit port size); and set the PCL bits to 00

(status input) or 01 (status input with interrupt). If the cycle steal with hold transfer mode

is selected, write to the GCR to select the required timeout. (See the GCR description in

Chapter 4 for recommended values.

d. Write to the OCR of Channel 1. Set the DIR bit to reflect the direction of transfer

(0=Memory-to-GPIB, 1=GPIB-to-Memory), set the SIZE bits to 00 (byte), set the

CHAIN bits to 10 or 11 (array or linked chaining), and set the REQG bits to 10 (REQ*

line initiates transfer). The array chaining feature is usually used to implement the carry

cycle because of its simplicity.

e. Set the SCR of Channel 1 to 00 (addresses do not count).

f. For array or linked chaining, load the BFCR of Channel 1 with the proper value to

generate the required address modifier code, which then accesses the address & transfer

count array. (See Tables 3-1 and 3-2 for recommended values.)

g. For array or linked chaining, load Channel 1 BAR with the beginning address of the

address & transfer count array.

h. For array chaining, load the BTCR of Channel 1 with 2 (two entries in the carry cycle

array). Linked chaining does not use the BTCR.