Chapter 4 Register Descriptions
© National Instruments Corporation 4-59 GPIB-1014 User Manual
Bit Mnemonic Description
4r/w ERR Error Bit
The Error bit is used to report the occurrence of error conditions. It is
set if any errors have been signaled. If bit ERR is set, the CER logs
the exact cause of the error. If this bit is cleared, the CER is also
cleared.
0 = No errors
1 = Error as coded in CER
3r/w ACT Channel Active Bit
The Channel Active bit is asserted after the channel has been started.
The bit remains set until the channel operation terminates. This bit is
unaffected by write operations.
0 = Channel not active
1 = Channel active
2r/w 0 Reserved Bit
Write zero to this bit.
1r/w PCT Peripheral Control Transition Bit
The Peripheral Control Transition bit is set if a falling edge transition
has occurred on the Peripheral Control Line (PCL) of the channel.
0 = No PCL transition occurred
1 = High-to-low PCL transition occurred
0r/w PCS Peripheral Control Status Bit
The Peripheral Control Status reflects the state of the channel's PCL.
This bit is unaffected by write operations.
0 = PCL low
1 = PCL high