Diagnostic and Troubleshooting Test Procedures Chapter 7
GPIB-1014 User Manual 7-8 © National Instruments Corporation
3000 data = 0000 clear two memory locations, these will be written
over by data from GPIB
3002 data = 0081 clear memory location 3002 as it will be written
over and put carry cycle byte (81 = HLDA) in
location 3003
3004 data = 0000 define carry cycle array's first entry
3006 data = 3003 4-byte address of carry cycle byte (00003003)
3008 data = 0001 first entry's transfer count (0001)
300A data = 0000 define carry cycle array's second entry
300C data = 3002 4-byte address of last data byte (00003002)
300E data = 0002 second entry's transfer count (0002)
105 CFG2 = 0A Set LMR and turn LED green
105 CFG2 = 08 Clear LMR
101 CFG1 = 1D BRG3*, IN, CC, enable ROR feature
004 DCR0 = A0 Configure DMAC
044 DCR1 = A0
005 OCR0 = 82
045 OCR1 = 8A
006 SCR0 = 04
046 SCR1 = 04
029 MFC0 = 06
00C MAR0 = 00003000 4-byte address of the first two data bytes
00A MTC0 = 0002 two data bytes
069 MFC1 = 06
079 BFC1 = 06
05C BAR1 = 00003004 4-byte address of the carry cycle array
05A BTC1 = 0002 carry cycle array has two entries - two small
memory blocks to be transferred
000 CSR0 = FF
040 CSR1 = FF
11B AUXMR = 2 TLC Reset
119 ADMR = C0 ton,lon
115 IMR2 = 10 DMA in enable
047 CCR1 = 80 start channel 1
007 CCR0 = 80 start channel 0
11B AUXMR = 0 Immediate execute pon
113 ISR1 = 2? check if DI is cleared before write data byte to DIR
111 DIR = 1 write first data byte to TLC, since DIR is full, TLC
will request for a DMA transfer to put the byte in
DIR to memory
113 ISR1 = 2? after transferred the first data byte, check if DI is
cleared before write second byte to DIR
111 DIR = 2 write second data byte to TLC, since DIR is full,
TLC will request for a DMA transfer to put the byte
in DIR to memory
000 CSRO = 81? channel 0 finished (COC)