Serial Poll Status Register (SPSR)VMEbus Address: Base Address + 117 (hex)
Attributes: Read Only, Internal to TLC
Serial Poll Mode Register (SPMR)VMEbus Address: Base Address + 117 (hex)
Attributes: Write Only, Internal to TLC
R
W
7 654 3210
S8
S8 PEND
rsv S6
S6 S5
S5 S4
S4 S3
S3 S2
S2 S1
S1
Bit Mnemonic Description
7r S8 Serial Poll Status Bit 8
7w,
5-0r, S[6-1] Serial Poll Status Bits 6 through 1
5-0w Cleared by Power On Reset (pon), and by issuing the Chip Reset
auxiliary command. These bits are used for sending device- or
system-dependent status information to the GPIB when the TLC is
serial polled. When the TLC is addressed as the GPIB Talker and
receives the GPIB multiline Serial Poll Enable (SPE) command
message, the TLC transmits a byte of status information, SPMR[7- 0],
to the Controller-In-Charge after the Controller goes to standby and
becomes an Active Listener.
6r PEND Pending Bit
PEND is set when rsv=1 and cleared when the Negative Poll Response
State (NPRS) & Request Service (rsv) = 1. Reading the PEND status
bit can confirm that a request was accepted and that the Status Byte
(STB) was transmitted (PEND=0).
6w rsv Request Service Bit
The rsv bit is used for generating the GPIB local rsv message. When
rsv is set and the GPIB Active Controller is not serial polling the TLC,
the TLC enters the Service Request State (SRQS) and asserts the GPIB
SRQ signal. When the Active Controller reads the STB during the
poll, the TLC clears rsv at the Affirmative Poll Response State
(APRS). The rsv bit is also cleared by pon, and by issuing the Chip
Reset auxiliary command.