Chapter 4 Register Bit Descriptions
© National Instruments Corporation 4-11 GPIB-1014 User Manual
Bit Mnemonic Description
SCG: GPIB Secondary Command Group
ACDS: GPIB Accept Data State
pon: Power On Reset
Read ISR1: Bit is cleared immediately after it is read
The APT bit indicates that a secondary GPIB address has been
received and is available in the CPTR for inspection
Note: The application program must check this bit when using TLC
address mode 3.
When APT is set, the Data Accepted (DAC) message is held and the
GPIB Handshake stops until either the Valid or Non-Valid auxiliary
command is issued. The secondary address can be read from the
CPTR.
5r DET Device Execute Trigger Bit
5w DET IE Device Execute Trigger Interrupt Enable Bit
DET is set by:
DTAS
DET is cleared by:
pon + (read ISR1)
Notes
DTAS: GPIB Device Trigger Active State
pon: Power On Reset
read ISR1: Bit is cleared immediately after it is read
The DET bit indicates that the GPIB Device Execute Trigger (DET)
command has been received while the TLC was a GPIB Listener (the
TLC has been in DTAS).
4r END RX End Received Bit
4w END IE End Received Interrupt Enable Bit
END RX is set by:
LACS & (EOI + EOS & REOS) & ACDS
END RX is cleared by:
pon + (read ISR1)
Notes
LACS: GPIB Listener Active State
EOI: GPIB End Of Identify Signal