Chapter 4 Register Bit Descriptions
© National Instruments Corporation 4-13 GPIB-1014 User Manual
Bit Mnemonic Description
write CDOR: Bit is set immediately after writing to the
Command/Data Out Register
SDYS to SIDS: Transition from GPIB Source Delay State to Source
Idle State
pon: Power On Reset
read ISR1; Bit is cleared immediately after it is read
The ERR bit indicates that the contents of the CDOR have been lost.
ERR is set when data is sent to the GPIB without a specified Listener
or when a byte is written to the CDOR during SIDS or during the
SDYS to SIDS transition.
1r DO Data Out Bit
1w DO IE Data Out Interrupt Enable Bit
DO is set as:
(TACS & SGNS) becomes true
DO is cleared by:
(read ISR1) + TACS* + SGNS*
Notes
TACS: GPIB Talker Active State
SGNS: GPIB Source Generate State
read ISR1: Bit is cleared immediately after it is read
The DO bit indicates that the TLC is ready to accept another data byte
from the VMEbus for transmission on to the GPIB when the TLC is
the GPIB Talker. The DO bit is cleared when a byte is written to the
CDOR and also when the TLC ceases to be the Active Talker. When
performing a DMA operation, DO IE must be clear so that an interrupt
request does not occur. Instead, the DMA0 bit in the Interrupt Mask
Register 2 (IMR2[5]w) must be set to enable a DMA cycle request
when DO is asserted.
0r DI Data In Bit
0w DI IE Data In Interrupt Enable Bit Bit
DI is set by:
LACS & ACDS & continuous mode
DI is cleared by:
pon + (read ISR1) + (Finish Handshake) & (Holdoff mode) +
(read DIR)