Chapter 6 Theory of Operation
© National Instruments Corporation 6-11 GPIB-1014 User Manual
are some external requests for the bus. While the board is holding the bus and the DMAC
requests the bus, the DMAC is immediately granted the bus, thus avoiding bus arbitration time.
The circuitry consists of various components to drive and receive VMEbus signals BBSY*,
BR0* through BR3*, BG0IN* through BG3IN*, and BG0OUT* through BG3OUT*. An S139
2- to 4-bit decoder is used to select one of the four VMEbus Request/Grant lines. In addition, the
circuitry uses three flip-flops to keep status of the bus arbitration process (that is, bus request
pending, bus grant received, and bus release) and uses miscellaneous logic to generate various
combinational outputs. The operation and output of each flip-flop (Q1, Q2, and Q3) is shown in
Figure 6-1.
Q1 = 0
Q1 = 1
RESET* = 0
Q1
OWN* = 0 BR* = 0
Q2 = 1
Q2 = 0
RESET* = 0
Q2
BUS_REL* = 0 BGIN = 1
(or BUS_REL* = 0)
(and BR* = 0)
Q3 = 0
Q3 = 1
RESET* = 0
Q3
BUS_REL* = 0 OWN* = 0
(or BUS_REL* = 0)
(and BR* = 0)
Figure 6-1. DTB Requester and Controller Flip-Flop Operations
In Figure 6-1, BR* is asserted by the DMAC to request the use of the VMEbus. BGIN is
asserted by the DTB Requester and Controller circuitry when a correct bus grant signal is