National Instruments 320030-01 Address Register 0 (ADR0)

Register Descriptions Chapter 4

GPIB-1014 User Manual 4-42 © National Instruments Corporation

Address Register 0 (ADR0)

VMEbus Address: Base Address + 11D (hex)

Attributes: Read Only, Internal to TLC

76543210

X DT0 DL0 AD5-0 AD4-0 AD3-0 AD2-0 AD1-0

R

Address Register 0 (ADR0) reflects the internal GPIB address status of the TLC as configured

using the ADMR. In addressing mode 2, ADR0 indicates the address and enable bits for the

primary GPIB address of the TLC. In dual primary addressing (modes 1 and 3) ADR0 indicates

the TLC major primary GPIB address. Refer to the description of the Address Mode Register in

this section for information on addressing modes.

Bit Mnemonic Description

7r X Don't Care Bit

Reads as a zero or one.

6r DT0 Disable Talker 0 Bit

If DT0 is set, it indicates that the mode 2 primary (or mode 1 and 3

major) Talker is not enabled; that is, the TLC does not respond to a

GPIB talk address matching AD[5-0 – 1-0]. If DT0=0, the TLC

responds to a GPIB talk address matching bits AD[5-0 – 1-0].

5r DL0 Disable Listener 0 Bit

If DL0 is set, it indicates that the mode 2 primary (or mode 1 and 3

major) Listener is not enabled; that is, the TLC does not respond to a

GPIB listen address matching bits AD[5-0 – 1-0]. If DL0=0, the TLC

responds to a GPIB listen address matching bits AD[5-0 – 1-0].

4-0r AD[5-0 – 1-0] Mode 2 Primary TLC GPIB Address Bits 5-0 through 1-0

These are the lower five bits of the TLC GPIB primary (or major)

address. The primary talk address is formed by adding hex 40 to

AD[5-0 – 1-0], while the listen address is formed by adding hex 20.

Contents

Main Page Limited Warranty Copyright Trademarks Page FCC/DOC Radio Frequency Interference Compliance Federal Communications Commission Canadian Department of Communications Instructions to Users Contents Chapter 5 Programming Considerations Chapter 6 Theory of Operation Page Appendix F Mnemonics Key Appendix G Customer Communication Glossary Index Figures Tables About This Manual Organization of This Manual Conventions Used in This Manual Related Documentation Customer Communication Chapter 1 Introduction Page What Your Kit Should Contain Optional Equipment Unpacking Chapter 2 General Description Electrical Characteristics VMEbus Characteristics VMEbus Slave-Addressing VMEbus Slave-Data Table 2-3. 68450 Internal DMA Registers Ad (continues) VMEbus Master-Direct Memory Access Interrupter Data Transfer Bus (DTB) Requester Diagnostic Aids Data Transfer Features Programmed I/O Transfers GPIB-1014 Functional Description Chapter 2 General Description Figure 2-1. GPIB-1014 with a VMEbus Computer National Instruments Corporation 2-9 GPIB-1014 User Manual General Description Chapter 2 Figure 2-2. GPIB-1014 in a Multiprocessor Application GPIB-1014 User Manual 2-10 National Instruments Corporation Chapter 2 General Description National Instruments Corporation 2-11 GPIB-1014 User Manual Figure 2-3 is a block diagram of the GPIB-1014. Figure 2-3. GPIB-1014 Block Diagram Page Page Page Page Page Page Access Mode Base Address Page DMA Address Modifier Code Output Page Other Configuration Parameters Installation Verification of System Compatibility Configuration and Installation Chapter 3 GPIB-1014 User Manual 3-8 National Instruments Corporation Table 3-3. GPIB-1014 Pin Assignment on VMEbus Connector P1 Pin No. Signal Used Signal Not Used Pin No. Signal Used Signal Not Used Chapter 3 Configuration and Installation National Instruments Corporation 3-9 GPIB-1014 User Manual Table 3-4. GPIB-1014 Pin Assignment on VMEbus Connector P2 Signal Signal Signal Signal Pin No. Used Not Used Notes Pin No. Used Not Used Notes Notes Cabling Verification Testing Chapter 4 Register Bit Descriptions Register Map Register Sizes Register Description Page Interface Registers Figure 4-1. Interface Registers Figure 4-2. Writing to the Hidden Registers Data In Register (DIR) Command/Data Out Register (CDOR) Interrupt Status Register 1 (ISR1) Interrupt Mask Register 1 (IMR1) Page Page Page Page Page Interrupt Status Register 2 (ISR2) Interrupt Mask Register 2 (IMR2) Page Page Page Page Serial Poll Status Register (SPSR) Serial Poll Mode Register (SPMR) Address Status Register (ADSR) Page Address Mode Register (ADMR) Page Page Command Pass Through Register (CPTR) Page Auxiliary Mode Register (AUXMR) Page Page Page Page Page Hidden Registers Page Page Page Page Page Page Page Page Address Register 0 (ADR0) Address Register (ADR) Address Register 1 (ADR1) End of String Register (EOSR) DMA Registers Chapter 4 Register Descriptions Figure 4-3. DMA Register Memory Map National Instruments Corporation 4-47 GPIB-1014 User Manual Reprinted from the Motorola MC68440 Advance Information manual. Address Registers Transfer Count Registers Function Code Registers Device Control Register Page Operation Control Register Page Sequence Control Register Channel Control Register Page Channel Status Register Page Channel Error Register Channel Priority Register Interrupt Vector Registers General Control Register Configuration Registers Page Page Page Chapter 5 Programming Considerations Initialization Page The GPIB-1014 as GPIB Controller Becoming Controller-In-Charge (CIC) and Active Controller Sending Remote Multiline Messages (Commands) Going from Active to Standby Controller Going from Standby to Active Controller Going from Active to Idle Controller The GPIB-1014 as GPIB Talker and Listener Programmed Implementation of Talker and Listener Addressed Implementation of the Talker and Listener Page Sending/Receiving Messages Using Direct Memory Access Page Page Page Page Page Page Page Page Page Page Page Using Programmed I/O Interrupts Page Serial Polls Conducting a Serial Poll Responding to a Serial Poll Parallel Polls Conducting a Parallel Poll Responding to a Parallel Poll Chapter 6 Theory of Operation VMEbus Interface Data Lines Control Signals Address Control Equations of Transceivers Address Decoding Clock and Reset Circuitry Configuration Registers Configuration Register 1 Page Configuration Register 2 Timing State Machine Slave Cycles DMA Cycles DMA Gating and Control Interrupter DTB Requester and Controller Page Page GPIB Synchronization and Interrupt Control Page Page 68450 DMAC DMAC Channel Operation Page Page Page Page Page Page Page Page Page GPIB Interface Test and Troubleshooting DMA Stand-Alone Testing GPIB Interface Testing Page Chapter 7 Diagnostic and Troubleshooting Test Procedures Interpreting Test Procedures GPIB-1014 Hardware Installation Tests Page Page Page Page Page Page Page Appendix A Hardware Specifications Page Page Appendix C Sample Programs ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Multiline Interface Messages Hex Oct Dec ASCII Msg Hex Oct Dec ASCII Msg Message Definitions Multiline Interface Messages Hex Oct Dec ASCII Msg Hex Oct Dec ASCII Msg Appendix E Operation of the GPIB Types of Messages Talkers, Listeners, and Controllers The Controller-In-Charge and System Controller GPIB Signals and Lines Data Lines Handshake Lines Interface Management Lines Operation of the GPIB Appendix E GPIB-1014 User Manual E-4 National Instruments Corporation Physical and Electrical Characteristics Figure E-1. The GPIB Connector and Signal Assignments Page Configuration Requirements Related Documents Appendix F Mnemonics Key A B Page C D E F G H I L M N O P R S T Page Appendix G Customer Communication Technical Support Form ____________________________________________________ GPIB-1014 Hardware and Software Configuration Form National Instruments Products Other Products Page Documentation Comment Form Glossary ___________________________________________________ Index Numbers A B C D Page Page Page E F G H I Page J L M N O P Page R S Page T Page Page U V W