Programming Considerations Chapter 5
GPIB-1014 User Manual 5-14 © National Instruments Corporation
2. Channel 0 must be configured to provide a flyby transfer for the n-1 data bytes between the
GPIB and the VME system memory. The sequence is as follows:
a. Write the CCR of Channel 0 with the SAB bit set to abort the channel operation in case it
is still active.
b. Write a 0xFF (hex) to the CSR of Channel 0 to clear any remaining error or status bits.
c. Load the DCR of Channel 0 with the proper value to select the DMA transfer mode,
Cycle Steal without Hold or Cycle Steal with Hold. Set the DTYP bits to binary 10
(device with ACK*, implicitly addressed); set the DPS bit to 0 (8-bit port size); and set
the PCL bits to 00 (status input). If the Cycle Steal with Hold transfer mode is selected,
write the GCR to select the required timeout. (See the GCR description for
recommended values.)
d. The OCR of Channel 0 is written to. Set the DIR bit to reflect the direction of transfer
(0=Memory-to-GPIB, 1=GPIB-to-Memory). Set the SIZE bits to 00 (byte); set the
CHAIN bits to the desired value (00 if no chaining is used, 10 if array chaining is used,
11 if linked chaining is used), and set the REQG bits to 10 (REQ* line initiates transfer).
Chaining is used to transfer a block of data greater than 64K or to transfer multiple blocks
of data.
e. The SCR of Channel 0 is written to. Set the MAC bits to determine if the MAC counts
up or down (01=Up, 10=Down). The DAC bits are not used.
f. If no chaining is required, complete the following events:
• Load the MFCR of Channel 0 with the proper data to generate the required Address
Modifier Code to access the data buffer. See Tables 3-1 and 3-2 for recommended
values.
• Load the MAR of Channel 0 with the starting physical address of the buffer of data
that is to be transferred.
• Load the MTCR of Channel 0 with the number of bytes (n-1 total) in the buffer to be
transferred (must be less than or equal to 64K: 65536 or 0xFFFF hex).
g. If chaining is required, complete the following events:
Note: Chaining modes (array or linked) all use an address & transfer count array, which
is an array of pointers that point to the data blocks to be transferred.
• For array or linked chaining, load the BFCR of Channel 0 with the proper data to
generate the required Address Modifier Code to access the "address & transfer count"
array. See Tables 3-1 and 3-2 for recommended values.
• For array or linked chaining, load the BAR of Channel 0 with the starting physical
address of the address & transfer count array.
• For array chaining, load the BTCR of Channel 0 with the number of entries in the
address & transfer count array. Linked chaining does not use the BTCR.