Index
© National Instruments Corporation Index-2 GPIB-1014 User Manual
Memory Address Register (MAR), 4-48
theory of operation, 6-17
Address Status Register (ADSR), 4-20 to 4-21
addressed implementation of Talker and Listener, 5-6 to 5-8
ADM[1-0] (Address Mode Bits 1 through 0), 4-23 to 4-24
ADMR. See Address Mode Register (ADMR).
ADR. See Address Register (ADR).
ADR0. See Address Register 0 (ADR0).
ADR1. See Address Register 1 (ADR1).
ADSC (Addressed Status Change Bit), 4-17 to 4-18
ADSC IE (Addressed Status Change Interrupt Enable Bit), 4-17 to 4-18
ADSR. See Address Status Register (ADSR).
AM code output. See DMA address modifier code output.
ANSI/IEEE Standard 1014-1987, 1-1
APT (Address Pass-Through Bit), 4-9 to 4-10
APT IE (Address Pass-Through Interrupt Enable Bit), 4-9 to 4-10
array chaining operations, 6-19 to 6-20
ARS (Address Register Select Bit), 4-43
ATN* (Attention* Bit), 4-20
ATN (attention) line, E-3
auxiliary commands
detailed description, 4-29 to 4-32
summary table, 4-28
Auxiliary Mode Register (AUXMR)
command summary (table), 4-28
detailed description (table), 4-29 to 4-32
overview, 4-27
Auxiliary Register A (AUXRA), 4-37 to 4-38
Auxiliary Register B (AUXRB), 4-39 to 4-40
Auxiliary Register E (AUXRE), 4-41
B
BAR. See Base Address Register (BAR).
base address configuration
selecting base address, 3-3
setting with compare address lines, 3-4
setting with jumper block W1, 3-4
Base Address Register (BAR), 4-48
Base Transfer Counter Register (BTCR), 4-48
BIN (Binary Bit), 4-37
BR (Bandwidth Available to DMAC Bits 1 through 0), 4-63
BRG (Bus Request/Grant Bits), 4-65
BT (Burst Transfer Time Bits 3 through 2), 4-63
BTC (Block Termination Complete Bit), 4-58, 4-62, 6-19
BTCR. See Base Transfer Counter Register (BTCR).
bus signals. See VMEbus.