Index
GPIB-1014 User Manual Index-5 © National Instruments Corporation
VMEbus, 6-3
data or data messages, E-1
DATA SEND-DSEND sample program, C-14 to C-16
data transfer bus (DTB) requester
description of, 2-7
VMEbus modules not provided, 2-7
data transfer features. See also DMA data transfers.
programmed I/O transfers, 2-8
throughput, 2-7 to 2-8
DAV (data valid) signal, E-3
DCL (Device Clear) command, 4-25
DCR. See Device Control Register (DCR).
DEC (Device Clear Bit), 4-11
DEC IE (Device Clear Interrupt Enable Bit), 4-11
DET (Device Execute Trigger Bit), 4-10
DET IE (Device Execute Trigger Interrupt Enable Bit), 4-10
Device Address Register (DAR), 4-48
Device Control Register (DCR), 4-51 to 4-52
DHDC (DAC Holdoff on DCAS Bit), 4-41
DHDT (DAC Holdoff on DTAS Bit), 4-41
DI[7-0] (Data In Bits 7 through 0), 4-6
DI (Data In Bit), 4-12 to 4-13
DI IE (Data In Interrupt Enable Bit), 4-12 to 4-13
DIR. See Data In Register (DIR).
DIR (Direction Bit), 4-53, 4-65
Disable System Control command
codes for, 4-28
description, 4-32
DL (Disable Listener Bit), 4-43
DL0 (Disable Listener 0 Bit), 4-42
DL1 (Disable Listener 1 Bit), 4-44
DMA address modifier code output
configuration, 3-5 to 3-7
default settings of AM code jumpers W3, W4 and W5, 3-5
programming values for default settings W3, W4 and W5, 3-6
setting AM code bits (AM5-AM0), 3-6
DMA cycles, Timing State Machine, 6-7
DMA data transfers
Dual Address Transfers, 6-16
overview, 5-8 to 5-9
polling during DMAs, 5-17
sending END or EOS, 5-17
Single Addressing Mode, 6-16
terminating on END or EOS, 5-19
terminating transfer and checking results, 5-17 to 5-19
theory of operation, 6-16
VMEbus interface, 6-1
with carry cycle, 5-13 to 5-17
without carry cycle, 5-10 to 5-12