National Instruments 320030-01

Chapter 6 Theory of Operation

Device (TLC)/DMAC Communication. Communication between the TLC and the DMAC is

accomplished mainly by two signals. Each of the four DMA channels has a DMA request input

(REQ0* through REQ*3) and a DMA acknowledge output (ACK0* through ACK3*). The TLC

requests service by first asserting its DMAREQ line, waits for its DMAACK* pin to assert, and

finally waits for its RD* or WR* pins to assert before sending or receiving data. The DMA

Gating and Control circuitry gates the DMAREQ of the TLC to REQ0* or REQ1* depending on

if carry cycle function is used. Depending on which channel is being serviced, either the ACK0*

or the ACK1* line is activated during transfers to or from the TLC. This line is used to tell the

TLC its current DMA request is being serviced (the DMAACK* of the TLC is asserted).

Flowthrough memory-to-memory transfers must use the automatic request mode. The ACK*

line is not activated.

Each channel also has a peripheral control line (PCL0* through PCL3*). The function of this

line is quite flexible, and is programmable via the Device Control Register (DCR). The DTYP

bits of the DCR define what type of device is on the channel. If the DTYP bits are programmed

to be a HMCS6800 device, the PCL definition is ignored, and the PCL is an Enable Clock input.

If the DTYP bits are programmed to be a device with READY, the PCL definition is ignored and

the PCL is used as a READY input. The PCL is active at all times when it is programmed as a

Status input, Interrupt input, Ready input, or Enable input. When programmed as an Abort input,

it is only active after the channel has been started. When programmed as a Status input, like in

most GPIB-1014 applications, the status level of the PCL can be determined by reading the PCS

bit in the CSR (TTL high or low). If a negative transition occurs and remains stable for two

DMAC clock cycles (8 MHz), the PCT bit of the CSR is set. The setting of the PCT bit causes

an interrupt, if interrupts were previously enabled, by setting the EINT bit in CCR. The

GPIB-1014 uses the PCL of Channel 1 (PCL1*) to detect interrupts from the TLC, bus error, and

GPIB synchronization conditions. In addition, the board uses the PCLs of Channel 0 (PCL0*)

and Channel 2 (PCL2*) to detect the status of two GPIB signals: SRQ* and REN*. If they are

used in a GPIB-1014 application, these two PCLs must be programmed as Status input or

Interrupt input.