Theory of Operation Chapter 6
GPIB-1014 User Manual 6-26 © National Instruments Corporation
transfer, the Memory Address and Device Address Registers point to the location of the next
operand and the Memory Transfer Counter contains the number of operands yet to be transferred.
If an error occurs during a transfer, that transfer has not completed and the registers contain the
values they had before the transfer was attempted.
The DMAC logs the first error encountered in the Channel Error Register. If an error is pending
in the Error Register and another error is encountered, the second error will not be logged.
GPIB Interface
The GPIB-1014 is interfaced to the GPIB using an NEC µPD7210 Talker/Listener/Controller
(TLC) large scale integrated circuit. Access to the TLC is through a block of 16 VMEbus
addresses that access the internal TLC registers.
When the GPIB-1014 is operating as a VMEbus slave, the TLC is enabled (TLCCS* is asserted)
when the base address of the GPIB-1014 has been decoded and VMEbus address bit A8 is a
logic 1, and bit A4 is a logic 1. The TLC register select signals (RS2 through RS0) are derived
from VMEbus address lines A3 through A1. Data is strobed into the TLC registers using WR*.
Data is read from the TLC using RD*. Both RD* and WR* are generated by the Timing State
Machine and are derived from the VMEbus WRITE* line.
During DMA transfers, the GPIB-1014 is acting as the VMEbus master, and the TLCCS* and
RS2 through RS0 signals are ignored by the TLC (except when the carry cycle byte is written to
the Auxiliary Register by the DMAC). Instead, the chip is enabled and selected by the
DMAACK* (DMA Acknowledge) signal and the TLC internal registers, CDOR and DIR, are
automatically accessed. Data is strobed into the CDOR at the rising edge of the TLC WR*
signal. If RD* is asserted, data from the DIR is placed on the internal 3-state data bus a
minimum access time after DMAACK* is asserted low.
Most of the TLC GPIB interface functions can be implemented or activated from either side; that
is, the TLC can be programmed to do these functions by the VMEbus master or it can be
addressed to do them by the GPIB Controller. In terms of the IEEE 488 standard, the distinction
between these two modes of operation is generally the same as that between local and remote
interface messages, respectively, as defined in the standard.
The ADSR is the primary register for monitoring the current status of the TLC; that is, to
determine if it is a GPIB Talker, GPIB Listener, GPIB Active Controller, or in GPIB remote or
local mode. The CPTR provides a means to read the GPIB data bus directly and is used to
recognize interface messages that are not automatically decoded and implemented by the TLC.
The ADR is used to program the primary and secondary GPIB addresses of the TLC and is also
used to disable talking or listening and to enable dual primary addressing. The SPMR is used to
program the serial poll status byte.
IMR1 and IMR2 are Interrupt Mask Registers for enabling and disabling the interrupt from the
TLC on the occurrence of 13 key GPIB conditions or events. The status of these conditions can
be read from the ISR1 and ISR2. The status bits in these registers function independently of the
corresponding mask bits; that is, they are set and cleared regardless of whether an interrupt