National Instruments 320030-01

Chapter 5 Programming Considerations

In cycle steal without hold mode, upon receiving a DMA request from the TLC, the DMAC

requests use of the VMEbus. Once the VMEbus is granted to the GPIB-1014, the DMAC

performs the DMA transfer. Then it immediately releases the bus.

In cycle steal with hold mode, after performing a DMA transfer, the DMAC will hold the

VMEbus for a programmable time period waiting for another DMA request. If no DMA request

is received from the TLC in the time period specified, the DMAC will relinquish ownership of

the VMEbus. If a DMA request is received from the TLC in the time period specified, the

DMAC performs the transfer immediately. The hold option is provided to reduce the VMEbus

arbitration time during GPIB transfers.

The onboard TLC acts as a buffer between the VMEbus memory and the GPIB. When the TLC

is a GPIB Talker and its CDOR is empty, the TLC asserts the DMA request line. The DMAC, in

response to the DMA request, transfers data from VMEbus memory to the CDOR. The TLC

then performs the necessary handshake sequence to transfer the byte to all GPIB Listeners.

Similarly, when the TLC is a Listener and a byte of received data is in the DIR, the TLC asserts

the DMA request line. The DMAC then transfers the data from the DIR to VMEbus memory.

The GPIB-1014 also provides the VMEbus Release On Request feature. This feature, which is

enabled in CFG1, causes the board to hold onto the VMEbus as long as no other board requests

the VMEbus. Even after the DMAC has relinquished the bus, the board still asserts VMEbus

signal BBSY* to hold onto the bus. If there is a DMAREQ while the board is holding the bus,

the DMAC is re-granted the bus immediately to start the next DMA transfer. If the board is

holding the bus and if some other device requests the bus, the GPIB-1014 will immediately

release the bus.

The two DMAC channels used by the GPIB-1014 are channels 0 and 1. The DMAC can be

configured to transfer data between the GPIB TLC and the VMEbus system memory with or

without the carry cycle feature. This feature is enabled in CFG1. During a DMA transfer from

the VMEbus memory to the GPIB, the carry cycle feature is used to make the TLC send the EOI

bit active with the last byte of data. During a DMA transfer from the GPIB to the VMEbus

memory, the carry cycle feature is used to make the TLC hold off the GPIB handshake sequence

after the last byte has been accepted by all GPIB Listeners.

Channel 0 is used to control the transfer of the entire block (n bytes) of data when the carry cycle

feature is not selected. If the carry cycle feature is used, Channel 0 is used to control the transfer

of the first (n-1) bytes of data. Then Channel 1 is used to transfer one byte of data (the carry

cycle byte) from the VME system memory to the TLC Auxiliary Register, and to transfer the last

(nth) byte of data. The carry cycle byte must be written to the TLC just prior to the last data byte

in order to instruct the TLC to handle the last byte as needed (to send EOI or holdoff handshake).

The carry cycle byte is just a TLC auxiliary command that is inserted in the n-byte transfer.

There is a slight preparation process you need to do if you use the carry cycle (See DMA

Transfers with a Carry Cycle later in this chapter.)

After the GPIB-1014 has transferred n bytes of data, it then automatically detects for GPIB

handshake synchronization, that is, if all Listeners have accepted the data. This synchronization

signal, along with interrupt signals from the TLC and VMEbus signal BERR*, are all routed to a

pin (PCL1) on the DMAC. If enabled for interrupt, the assertion of any of these three signals

sets the pin and the DMAC asserts an interrupt request line on the VMEbus. Thus, you can set

up and start the DMA transfer, then simply wait for a GPIB synchronization interrupt (if

interrupts are not enabled, polling is possible). This indicates n bytes have been transferred and

the GPIB handshake is synchronized.