Chapter 4 Register Descriptions
© National Instruments Corporation 4-39 GPIB-1014 User Manual
Auxiliary Register B (AUXRB)
VMEbus Address: Base Address + 11B (hex)
AUXMR Control Code: 101 (Binary, Bits 7 - 5)
Attributes: Write Only, Internal to TLC
Accessed through AUXMR
43210
W
ISS INV TRI SPEOI CPT
ENABLE
Writing to Auxiliary Register B (AUXRB) is done via the AUXMR. Writing the value 101 into
the Control Code (CNT[2-0]) and a bit pattern into the Command Code portion (COM[4-0]) of
the AUXMR causes the Command Code to be written to AUXRB. When the data is written to
AUXRB, the bits are denoted as shown in the figure above. This 5-bit code affects several
interface functions, as described in the following paragraphs.
Bit Mnemonic Description
4w ISS Individual Status Select Bit
The ISS bit determines the value of the TLC ist message. When
ISS=1, ist becomes the same value as the TLC Service Request State
(SRQS). (The TLC is asserting the GPIB SRQ message when it is in
SRQS.) When ISS=0, ist takes on the value of the TLC Parallel Poll
Flag. The Parallel Poll Flag is set and cleared using the Set Parallel
Poll Flag and Clear Parallel Poll Flag auxiliary commands.
3w INV Invert Bit
The INV bit affects the polarity of the TLC INT pin. Setting INV
causes the polarity of the Interrupt (INT) pin on the TLC to be active
low. As implemented on the GPIB-1014, configuring the INT pin to
active low results in interrupt request errors. Consequently, INV must
always be cleared and must never be set except for diagnostic
purposes.
INV = 0 : INT pin is active high
INV = 1 : INT pin is active low