National Instruments 320030-01

Chapter 5 Programming Considerations

b. A 0xFF (hex) must be written to the CSR of Channel 0 to clear any leftover error or

status bits.

c. The DCR of Channel 0 is loaded with the proper value to select the DMA transfer mode

(cycle steal without hold or cycle steal with hold). The DTYP bits should be set to binary

10 (device with ACK*, implicitly addressed), the DPS bit must be set to 0 (8-bit port

size), and the PCL bits should be set to binary 000 (status input). If the cycle steal with

hold transfer mode is selected, the GCR must be written to select the required timeout.

(See the GCR description for recommended values.)

d. Write to the OCR of Channel 0. The DIR bit must be set to reflect the direction of

transfer (0=Memory to GPIB, 1=GPIB to Memory). The SIZE bits should be set to

binary 00 (byte); the CHAIN bits should be set to the desired value (binary 00 if no

chaining is used, binary 10 if array chaining is used, binary 11 if linked chaining is used),

and the REQG bits should be set to binary 10 (REQ* line initiates transfer). Chaining is

used to transfer a block of data greater than 64K or to transfer multiple blocks of data.

e. Write to the SCR of Channel 0. The MAC bits must be set to determine if the MAC

counts up or down (binary 01=Up, binary 10=Down). The DAC bits are not used.

f. If no chaining is required, complete the following events:

• Load the MFCR of Channel 0 with the proper data to generate the required Address

Modifier Code to access the data buffer. See Tables 3-1 and 3-2 for recommended

values.

• Load the MAR of Channel 0 with the starting physical address of the buffer of data

that is to be transferred.

• Load the MTCR of Channel 0 with the number of bytes in the buffer to be transferred

(must be less than or equal to 64K).

g. If chaining is required, complete the following events:

Note: Chaining modes (array or linked) use an address & transfer count array, which is

an array of pointers that point to the data blocks to be transferred.

1. For array or linked chaining, load the BFCR of Channel 0 with the proper data to

generate the required Address Modifier Code to access the address & transfer count

array. See Tables 3-1 and 3-2 for recommended values.

2. For array or linked chaining, load the BAR of Channel 0 with the starting physical

address of the address & transfer count array.

3. For array chaining, load the BTCR of Channel 0 with the number of entries in the

address & transfer count array. Linked chaining does not use BTCR.