Theory of Operation Chapter 6
GPIB-1014 User Manual 6-24 © National Instruments Corporation
Start of arrayBAR
BTC
DMAC
Data Block
A
Data Block
B
Data Block
C
Address and
Transfer Count Array Data Blocks
xxxx (not used)
Memory Address A
Transfer Count A
Link to next entry
Memory Address B
Transfer Count B
Link to next entry
Memory Address B
Transfer Count B
0000 (end link)
Figure 6-3. Array Format for Linked Chaining Modes
Error Conditions. When an error is signaled on a channel, all activity on that channel is stopped.
The ACT bit of the CSR is cleared, and the COC bit is set. The ERR bit of the CSR is also set,
and the error code is recorded in the CER. All pending operations are cleared, so that both the
STR and CNT bits of the CCR are cleared.