Register Bit Descriptions Chapter 4
GPIB-1014 User Manual 4-12 © National Instruments Corporation
Bit Mnemonic Description
EOS: GPIB END Of String message
REOS: Reception of GPIB EOS allowed, AUXRA[2]w
ACDS: GPIB Accept Data State
pon: Power On Reset
read ISR1: Bit is cleared immediately after it is read
The END RX bit is set when the TLC is a Listener and the GPIB
uniline message, END, is received with a data byte from the GPIB
Talker, or the data byte in the DIR matches the contents of the End Of
String Register (EOSR).
3r DEC Device Clear Bit
3w DEC IE Device Clear Interrupt Enable Bit
DEC is set by:
DCAS
DEC is cleared by:
pon + (read ISR1)
Notes
DCAS: GPIB Device Clear Active State
pon: Power On Reset
read ISR1: Bit is cleared immediately after it is read
The DEC bit indicates that the GPIB Device Clear (DCL) command
has been received or that the GPIB Selected Device Clear (SDC)
command has been received while the TLC was a GPIB Listener (the
TLC is in DCAS).
2r ERR Error Bit
2w ERR IE Error Interrupt Enable Bit
ERR is set by:
TACS & SDYS & DAC & RFD + SIDS & (write CDOR) +
(SDYS to SIDS)
ERR is cleared by:
pon + (read ISR1)
Notes
TACS: GPIB Talker Active State
SDYS: GPIB Source Delay State
DAC: GPIB Data Accepted message
RFD: GPIB Ready For Data message
SIDS: GPIB Source Idle State