Programming Considerations Chapter 5
GPIB-1014 User Manual 5-18 © National Instruments Corporation
• An interrupt from the TLC
• A bus or DMAC error that occurred during a DMA transfer
• GPIB handshake synchronization
To determine which condition caused the interrupt, you must first examine the CSR of Channel
1. If the ERR bit of Channel 1 is set, a DMAC error occurred while Channel 1 was transferring
data. The CER of Channel 1 indicates the type of error that occurred. If Channel 1 is improperly
programmed, its operation terminates automatically and the ERR bit is set. This does not cause
an interrupt, but rather a timeout error in your program. The cause of the error can be found by
examining the CER of Channel 1. See the CER register description in Chapter 4 for more
information. If the ERR bit of Channel 1 is zero and its PCT bit is a one (which is the usual
case), one of the following conditions has occurred:
• A bus error has occurred while Channel 0 is transferring data.
• The TLC is interrupting.
• Synchronization on the GPIB is detected.
If a Channel 0 bus error has occurred, the ERR bit is set in the CSR of Channel 0 and the CER of
Channel 0 indicates a bus error.
Note: A bus error on Channel 0 will set the PCT bit in the CSR of Channel 1 but will not set the
ERR bit. Instead, it sets the ERR bit in the CSR of Channel 0. A timeout error (no
interrupt) occurs if Channel 0 is improperly programmed.
If the PCT bit in Channel 1 is set and there are no errors on Channel 0 or 1, one of the following
events has occurred:
• The TLC is interrupting.
• The DMA operation is complete and GPIB synchronization is detected.
The TLC should be examined for interrupt conditions (if TLC interrupts are enabled). This can
be done by examining the INT bit in ISR2. Since reading ISR1 can clear the INT bit in ISR2,
ISR2 should always be read before ISR1. If the TLC did not request an interrupt, the PCL
transition was caused by the GPIB becoming synchronized. To ensure that the DMA transfer
was completed, the CSR of Channel 0 must always be examined. The COC bit must be set and
the ERR bit should be cleared. This check is sufficient if the carry cycle feature was not used.
If the carry cycle feature was used, the CSR of Channel 1 must also be examined. The Channel
Operation Complete (COC) bit in Channel 1 must not be set, and the MTCR must contain a 1
because the second entry of the carry cycle array requests a 2-byte DMA transfer, but only one
byte (the nth data byte) is permitted to transfer. A 2-byte transfer is requested for the following
reason: If Channel 1 was permitted to reach terminal count (by requesting a 1-byte transfer), the
COC bit would set and an interrupt would occur (the DMAC interrupts if either the COC bit or
the PCT bit is set). It is necessary for the COC to detect if the nth byte has been transferred and