Theory of Operation Chapter 6
GPIB-1014 User Manual 6-12 © National Instruments Corporation
received. OWN* is asserted by the DMAC to indicate that it now has ownership of the bus.
BUS_REL* is asserted by the DTB Requester and Controller circuitry to indicate that it is going
to release the VMEbus. RESET* is asserted to reset all circuitry on the board.
Based on the output of the flip-flops, there are numerous combinational outputs. The following
equations contain these outputs:
Equation 1: LBROUT* = Q3 + Q1'
Equation 2: BG* = (BUS_REL* & Q1 & (MY_BGIN + OWNBUS))'
Equation 3: BGACK* = BBSY* + BGIN'
Equation 4: BGMATCH* = Q2 & BGIN
Equation 5: OWNBUS* = Q3'
BBSY* = Q3'
Equation 6: BUS_REL* = [ (ROR*+BRIN) & LBROUT* & OWN* & BR* & DEN* &
BGIN']'
In Equation 1, combinational output LBROUT* is asserted if DMAC has a bus request pending
and the board does not have control of the VMEbus. While the GPIB-1014 is holding the bus
and there is a request from the DMAC, LBROUT* (and thus BGIN) will not be asserted. BG*,
an input to the DMAC, is asserted to inform the DMAC that it has been granted the bus. Even
with its BG* asserted, the DMAC will not assert OWN* and start DMA cycle until BGACK* is
released (unasserted). Equation 3 indicates that if the board has been granted the bus (BGIN
asserted), BGACK* is released as soon as BBSY* is released by another master on the VMEbus.
While the GPIB-1014 is holding the bus, BGACK* will be released at all times. If a pending
DMAC bus request is acknowledged with a BGIN, BGMATCH* is asserted to maintain the
appropriate BGXOUT* high. When the GPIB-1014 does not request for the bus, BGMATCH*
is unasserted to pass BGXIN* directly to BGXOUT* (through the daisy chain). OWNBUS* and
BBSY* are both asserted when the GPIB-1014 is using control or is holding control of the bus.
If the Release On Request feature is not enabled (ROR*=1), BUS_REL* is asserted to release
the bus right after the DMAC has finished with its cycle and released OWN*. If the ROR feature
is enabled (ROR*=0) and the board is simply holding the bus (OWN*, BR*, and LBROUT* all
released), the board releases the bus as soon as there is an external bus request (BRIN asserted).
Finally, BUS_REL* is asserted to release the VMEbus after the board has released the data bus
and the arbiter has released its BGx*.
A typical bus arbitration process is described as follows:
1. The DMAC indicates that it needs the bus for a DMA transfer by driving its BR* pin low.
2. Two bits in CFG1 are used to select one of four VMEbus Bus Request/Grant lines. A
74S139 decoder is used to decode these two bits.
3. Because the board does not have control of the bus, LBROUT* is driven low.