Register Descriptions Chapter 4
GPIB-1014 User Manual 4-36 © National Instruments Corporation
Bit Mnemonic Description
3w S Status Bit Polarity (Sense) Bit
The S bit is used to indicate the polarity (or sense) of the TLC local ist
message. If S=1, the status is in phase, meaning that if, during a
Parallel Poll response, S=ist=1, and U=0, the TLC responds to the
Parallel Poll by driving one of the eight GPIB DIO lines low, thus
asserting it to a logic one. If S=1 and ist=0, the TLC does not drive the
DIO line.
If S=0, the status is in reverse phase, meaning that if, during a Parallel
Poll, ist=0, and U=0, the TLC responds to the Parallel Poll by driving
one of the eight GPIB DIO lines low. If S=0 and ist=1, the TLC does
not drive the DIO line.
For more information, refer to Auxiliary Register B and the Clear
Parallel Poll Flags/Set Parallel Poll Flags later in this section.
2-0w P[3-1] Parallel Poll Response Bits 3 through 1
PPR bits 3 through 1, designated P[3-1], contain an encoded version of
the Parallel Poll response. P[3-1] indicate which of the eight DIO lines
is asserted during a Parallel Poll (equal to N-1). The GPIB-1014
normally drives the GPIB DIO lines using three-state drivers. During
Parallel Poll responses, however, the drivers automatically convert to
Open Collector mode, as required by IEEE 488. For example, if
P[3-1]=010 (binary), GPIB DIO line DIO3* is driven low (asserted) if
the GPIB-1014 is parallel polled (and S=ist).
Table 4-6 contains some examples of configuring the Parallel Poll Register.
Table 4-6. Examples for Configuring the PPR
Written to the AUXMR
76543210 Result
01110000 Unconfigures PPR
01100000 0 0 0 0 0 is written to the PPR. The GPIB-1014D participates
in a Parallel Poll, asserting the DIO1 line if ist=0. Otherwise,
the GPIB-1014D does not participate.
01101001 0 1 0 0 1 is written to the PPR. The GPIB-1014D participates
in a Parallel Poll, asserting the DIO2 line if ist=1. Otherwise,
the GPIB-1014D does not participate.