National Instruments 320030-01 Configuration Registers

Chapter 6 Theory of Operation

control the timing of local signal DTACK* when the board is a slave and signal to control RD*

and WR* to the TLC (see Timing State Machine later in this chapter).

The VMEbus signal SYSRESET* is monitored by the GPIB-1014. It is received with an LS240

receiver and is ORed with the LMR bit in CFG2 to generate the onboard RESET signal. The

RESET signal is used to initialize all circuitry on the GPIB-1014 except the two bits in CFG2

(LMR and SYSFAIL*), the Address Decoding circuitry, and the DTACK* generation circuitry.

BRDEN* circuitry (refer to the Address Decoding section earlier in this chapter). The two bits in

CFG2 are reset only by the SYSRESET* signal or by a write to CFG2. The Address Decoding

and DTACK* generation circuitry can only be reset by SYSRESET*.

The VMEbus signal BERR* is monitored by the GPIB-1014 while it is bus master. This signal

is received by a 74LS241 receiver and is ANDed with the onboard signal OWN*, which is active

while the GPIB-1014 is bus master. If BERR* is driven active during a DMA transfer, the

DMAC input BEC1 is driven low, indicating to the DMAC that the cycle cannot be completed.

The DMAC responds to this condition by terminating the cycle and indicating a bus error

condition in the channel CER.

Configuration Registers

Two registers, CFG1 and CFG2, are 8-bit write-only registers used by the controlling software

program (application program and/or interface handler) to configure some of the operating

characteristics of the GPIB-1014.

A 74LS273 octal D-type flip-flop and an LS74A are used to implement Configuration Register 1

(CFG1). Data is written into each register on the rising edge of the WR* signal generated by the

Timing State Machine circuitry. Except for the ROR* bit, all other bits in CFG1 are cleared by

the onboard RESET* signal generated by the Clock and Reset circuitry. This write-only register

is used for a variety of configuration functions, including the following functions:

• Selecting the VMEbus Interrupt Request Priority for the GPIB-1014. The three most

significant bits are used to encode the desired interrupt priority. This encoded value is used

by the Interrupter circuitry to drive the appropriate VMEbus Interrupt Request line and to

identify an interrupt acknowledge cycle of the proper priority.

• Selecting the VMEbus Bus Request/Grant line. Two bits are used to encode the desired

VMEbus Bus Request/Grant line. This encoded value is used by the DTB Requester and

Controller circuitry to drive the appropriate Bus Request line and to monitor the appropriate

Bus Grant In line.

• Enabling the automatic carry cycle feature. Writing a 1 to this bit (CC) enables the carry

cycle feature while writing a zero disables the carry cycle feature. This bit is used by the

DMA Gating and Control circuitry.