Theory of Operation Chapter 6
GPIB-1014 User Manual 6-16 © National Instruments Corporation
4. Clear IMR2.
5. Write a value to CFG1 to release PCL1 line (perhaps use the same value as the last write to
CFG1).
6. Write a software abort to Channel 0.
7. Check, then clear the COC and ERR bits in CSR0.
8. Write a software abort to Channel 1 (if a carry cycle is used).
9. Check, then clear the PCT and ERR bits in CSR1.
The third step can cause a transition on the PCL1 if the VMEbus BERR* line is driven low while
the DMAC is bus master, indicating that the cycle cannot be completed. This condition causes
the DMAC BEC1* line to go low, which causes the DMAC to terminate the cycle and sets the
COC and ERR bits in the CSR of the active channel. Whether or not a carry cycle was used, a
bus error also causes a transition on the PCL of Channel 1, requesting an interrupt on Channel 1.
The host CPU can detect the error condition by examining the CSR of Channels 0 and 1.
68450 DMAC
The DMAC is a high-performance device and is very flexible. It provides four independent
DMA channels, but the GPIB-1014 uses only Channels 0 and 1 to provide GPIB-to-memory
DMA flyby transfers. All four channels are available for general use such as
memory-to-memory DMA transfers. The DMAC provides 24-bit addressing, a 16-bit data path,
and programmable selection of the address modifier lines. During DMA operations, the GPIB-
1014 functions as a full VMEbus master. The DMAC controls the direction of the GPIB-1014
data bus transceivers as needed to effect the transfer. Details of the DMAC operation, with
emphasis on GPIB-1014 applications, are given in the following section.

DMAC Channel Operation

A DMAC channel operation proceeds in three principal phases. During the initialization phase,
the CPU configures the channel control registers, sets initial addresses, and starts the channel.
During the transfer phase, the DMAC accepts requests for data operand transfers, and provides
addressing and bus controls for the transfers. The termination phase occurs after the operation is
completed when the DMAC reports the status of the operation. The following sections discuss
these three phases of the channel operation.
Initialization and Transfer Phases
The following paragraphs describe the communication between the TLC (the device) and the
DMAC as well as specific details on how the DMAC controls the data transfer during DMA
operations.