Register Bit Descriptions Chapter 4
GPIB-1014 User Manual 4-14 © National Instruments Corporation
Interrupt Status Register 2 (ISR2)VMEbus Address: Base Address + 115 (hex)
Attributes: Read Only, Internal to TLC
Bits are cleared when read
Interrupt Mask Register 2 (IMR2)VMEbus Address: Base Address + 115 (hex)
Attributes: Write Only, Internal to TLC
R
W
7 654 3210
INT
0SRQI
SRQI IE LOK
DMAO REM
DMAI CO
CO IE LOKC
LOKC IE REMC
REMC IE ADSC
ADSC IE
The Interrupt Status Register 2 (ISR2) consists of six Interrupt Status bits and two TLC Internal
Status bits. The Interrupt Mask Register 2 (IMR2) consists of five Interrupt Enable bits and two
TLC Internal Control bits. If the Interrupt Enable bit is true when the corresponding status
condition or event occurs, an interrupt request is generated. Bits in ISR2 are set and cleared
regardless of the status of the bits in IMR2. If a condition occurs that requires the TLC to set or
clear a bit or bits in ISR2 at the same time ISR2 is being read, the TLC holds off setting or
clearing the bit or bits until the read is finished.
Bit Mnemonic Description
7r INT Interrupt Bit
This bit is the logical OR of all the Enabled Interrupt Status bits in
both ISR1 and ISR2, each one ANDed with its Interrupt Enable bit.
There is no corresponding Mask bit for INT.
INT is set by:
(CPT & CPT IE) + (APT & APT IE) + (DET & DET IE) + ERR &
ERR IE) + (END RX & END IE) + (DEC & DEC IE) + (DO &
DO IE) + (DI & DI IE) + (SRQI & SRQI IE) + (REMC & REMC
IE) + (CO & CO IE) + (LOKC & LOKC IE) + (ADSC & ADSC
IE)
Notes
CPT: Command Pass Through Bit
CPT IE: Enable Interrupt on Command Pass Through Bit
APT: Address Pass Through Bit
APT IE: Enable Interrupt on Address Pass Through Bit
DET: Device Execute Trigger Bit
DET IE: Enable Interrupt on Device Execute Trigger Bit
ERR: Error Bit