© National Instruments Corporation 6-1 GPIB-1014 User Manual
Chapter 6Theory of Operation
This chapter contains a functional overview of the GPIB-1014 board and explains the operation
of each functional block making up the GPIB-1014.
A brief description of the GPIB-1014 interface is given in Chapter 2 along with a functional
block diagram (see Figure 2-4). The major elements of the GPIB-1014 are discussed in more
detail in this chapter with references to signals and circuits shown in the schematic diagram in
Appendix A.
Signal names in the following discussion are referenced in terms of logic value (true or false, and
asserted or not asserted), and also in terms of logic level (TTL high or low). Both positive and
negative logic symbols are used in the schematic diagram. The terms clear, negate, unassert,
reset, and set false are synonymous as are set, assert, and set true. Since in the circuit
implementation some positive true signals are derived from the inverted output of flip-flops,
these terms are not synonymous with the device signals CLR (clear) and PR (preset).

VMEbus Interface

Address, data, control, and status signals to or from the VMEbus are buffered with LSTTL,
ASTTL, or FTTL logic devices. All drivers drive the proper amount of current as required by
the VMEbus specification, and all receivers present the required bus load as called out by the
VMEbus specification.

Data Lines

Two F245 octal bus transceivers connect the VMEbus data lines (D15 through D00) to the
circuitry on the GPIB-1014. All 16 of these data lines are routed directly to the DMAC, while
only the lower eight data lines (D07 through D00) are connected to the 8-bit data bus of the TLC.
Slave Read and Write Transfers
During the slave read and write to the DMAC, both transceivers are enabled. In contrast, only
the lower 8-bit transceivers are enabled during accesses to the TLC or to the two onboard 8-bit
Configuration Registers. The GPIB-1014 drives the VMEbus data lines during onboard register
reads and receives (is driven by) the data on the VMEbus during onboard register writes.
DMA Transfers
During DMA transfers, the 8-bit data bus of the TLC can be directed to either the lower eight bits
(D7 through D0) or the upper eight bits (D15 through D08) of the VMEbus data bus. This is