National Instruments 320030-01 Address Registers

GPIB-1014 User Manual 4-48 © National Instruments Corporation

The following paragraphs describe the channel configuration and status registers. More

information on the 68450 can be found in the Motorola Semiconductor Technical Data

MC68450 Advance Information Direct Memory Access Controller (DMAC) or the Hitachi

Microcomputer System HD68450 DMAC (Direct Memory Access Controller). Each channel

contains the same status and configuration registers.

Address Registers

The Memory Address Register (MAR), Base Address Register (BAR), and Device Address

bits are connected to the address output pins.

The Memory Address Register (MAR) is used to hold the address of the VMEbus memory

location, which is where the data is transferred. This register is used in all DMA operations

(memory-to-memory or memory-to-device).

The Base Address Register (BAR) is used in continue, array chained, and link chained

operations. In continue mode of operation, the BAR holds the address of the next block of data

to be transferred. At the end of the last block transfer, the content of the BAR is automatically

transferred to the MAR and a next block transfer is started. In array chained and link chained

modes of operation, the BAR is used as a pointer to a table in memory which holds the

address(es) of the data block(s) to be transferred. Using the BAR in the chained modes of

operation, the DMAC first reads (using DMA) the address of the next block to be transferred into

the MAR, then starts the actual data transfer. In most GPIB-to-memory transfers, the array

chained mode of operation is used. For more information on this mode, see Sending/Receiving

Messages in Chapter 5 and Block Termination in Chapter 6.

The Device Address Register (DAR) is used to hold the device address when the DMA transfer

is in dual address (flowthrough) mode. This mode is used for devices that cannot be implicitly

addressed with an acknowledge (ACK) signal, but must be addressed via the address bus.

Flowthrough transfers address both the memory and the device by executing two bus cycles and

storing the data temporarily in an internal register. In single-address (flyby) transfers, the device

is implicitly addressed with an acknowledge signal, so that the data transfer takes one cycle and

the data is transferred directly between the device and memory. DMA transfers between the

GPIB and VMEbus memory use only flyby mode, so the device address register is not used.

General purpose memory-to-memory (flowthrough) transfers use both the MAR and DAR to

hold the source and destination VMEbus memory addresses.

While data transfers between the GPIB and VMEbus memory must use flyby mode,

memory-to-memory DMA transfers can be accomplished using any of the four available full-

function DMA channels (channels 0 to 3). This not only makes the GPIB-1014 available as a

general purpose VMEbus DMA Controller, but also enables comprehensive stand-alone

diagnostics to be performed on the DMA circuitry without using the GPIB.