Chapter 4 Register Descriptions

© National Instruments Corporation 4-47 GPIB-1014 User Manual

Register
Offset
00
02
04
06
08
0A
0C
0E
10
12
14
16
18
1A
1C
1E
20
22
24
26
28
2A
2C
2E
30
32
34
36
38
3A
3C
3E
15 0
Register
Offset
01
03
05
07
09
0B
0D
0F
11
13
15
17
19
1B
1D
1F
21
23
25
27
29
2B
2D
2F
31
33
35
37
39
3B
3D
3F
87
CSR CER
MTCR
MAR
MSB
LSB
DAR
MSB
LSB
BTCR
BAR
MSB
LSB
NIVR
EIVR
MFCR
CPR
DFCR
BFCR
Null Bit Position.
* The GCR is located at FF only.
Key
Channel
Base
CH0 - 00
CH1 - 40
CH2 - 80
CH3 - C0
DCR
SCR
OCR
CCR
GCR*
Note: The Register Address equals the Channel Base plus the Register Offset.

Reprinted from the Motorola MC68440 Advance Information manual.

Figure 4-3. DMA Register Memory Map