Theory of Operation Chapter 6
GPIB-1014 User Manual 6-2 © National Instruments Corporation
accomplished using an F245 8-bit data transceiver, which gates the upper data byte to the TLC.
This data transceiver is automatically controlled by the DMAC signal HIBYTE*. When the data
transfer is on VMEbus data lines D07 through D00, the HIBYTE* is not active and the TLC data
bus is connected to the lower eight bits of the VMEbus data bus. When the data transfer is on
VMEbus data lines D1 through D09, HIBYTE* is active and the TLC data bus is connected to
the upper eight bits of the VMEbus data bus. This feature allows the 8-bit GPIB data to be
packed in the 16-bit VMEbus memory. When the GPIB-1014 is acting as a VMEbus master, it
drives the VMEbus data lines on VMEbus memory writes, and receives from (is driven by) the
VMEbus data lines on VMEbus memory reads.
Control Signals
An F241 and F1241 buffer pair is used to transceive the data bus control signals AS*, WRITE*,
DS0*, and DS1*. The OWN* signal of the DMAC is used to control the direction of the buffer
pair. When the GPIB-1014 is a slave (that is, it does not have control of the bus), control signals
are directly routed onboard. In contrast, during DMA cycles, control signals from the DMAC are
somewhat altered before passing out to the VMEbus. For example, signal WRT* of the DMAC
is ORed with the onboard signal CCBYTE to implement the carry byte cycle (see DMA Gating
and Control in this chapter). The UDS* and LDS* signals of the DMAC are delayed by the
timing state machine output before being sent to the VMEbus (see Timing State Machine later in
this chapter). In addition, if DTACK* of BERR* from the last cycle is still asserted, a flip-flop
prevents the GPIB-1014 from driving the data bus, DS0* or DS1*.
Address
When the board is a VMEbus slave, information from the VMEbus address bus lines A15
through A9, the Address Modifier Lines AM5 through AM0, and the VMEbus signals IACK*
and LWORD* is received and decoded by two LS2521 8-bit comparators. (For more
information, see the Address Decoding section in this chapter.)
When the board is a VMEbus master, it drives the address lines (A23-A1), the address modifier
lines (AM5-AM1), IACK*, and LWORD*. The upper 16 bits of the address are driven by two
transparent D-type flip-flop AS573s while the lower eight bits are driven by an F245. The UAS*
signal of the DMAC is used to clock the AS573s.