National Instruments 320030-01

Chapter 6 Theory of Operation

Operands and Addressing. Three factors affect how the actual data is handled: device

(destination) port size, operand (from source) size, and address sequencing.

•Device Port Size The DCR is also used to program the device port size to be 8 or 16

bits. The port size is the number of data bits that the device can

handle (transmit or receive) in a single bus cycle. For GPIB DMA

data transfers, the device (or TLC) port size is eight bits. For

memory-to-memory transfers, the port size can be 8 or 16 bits.

•Operand Size The OCR is used to program the operand size to be either byte,

word, or longword. The operand size is the number of bits of data

to be transferred to honor a single DMA request. Multiple bus

cycles may be required to transfer the entire operand through the

device port if the operand is larger than the device port size. For

single-addressing operations, like GPIB DMA operations, the

device port size and the operand size must be equal. The transfer

counter counts the number of operands transferred. For GPIB

DMA data transfers, the operand size is eight bits and the transfer

counter indicates the number of bytes to be transferred. For

memory-to-memory transfers, the operand size can be byte, word,

or longword.

•Address Sequencing The sequence of addresses generated to address the memory and

device depends on the port size, operand size, whether the

addresses are to count up, down, or not change, and whether the

transfer is explicitly or implicitly addressed. The Sequence

Control Register (SCR) is used to program the memory address

count method and the device address count method.

For single-address transfers, such as GPIB DMA transfers, the device port size and operand size

must be equal. If the operand size is a byte, the address increment/decrement is one (1). If the

operand size is a word, the address increment is two (2). The Memory Address Register and the

transfer counter are updated after the operand is transferred.

For dual-address transfers (memory-to-memory), the device port size or the memory width need

not equal the operand size. The DMAC will run multiple bus cycles to transfer operand parts

until the entire operand has been transferred. Regardless of the way the address register is

counting (up or down), the DMAC accesses the parts of the operand in a linear increasing

sequence. The step between the addresses of the parts is two. The size of the parts is of course

the size of the device port or memory width. The number of parts is the operand size divided by

the port size or memory width. The address increment is added or subtracted after the operand is

transferred.

Address Register Operation. The DMAC has three 32-bit address registers per channel: the

Memory Address Register (MAR), Device Address Register (DAR), and the Base Address

and a device. This register is either initialized before the channel operation is started, or is

loaded during chaining or continue operations, which are discussed later. The DAR is used to