National Instruments 320030-01

Chapter 5 Programming Considerations

accepted by all Listeners on the GPIB (indicating a GPIB synchronization). For this reason,

Channel 1 is programmed to transfer two bytes to avoid a premature COC interrupt. After the

last data byte (the nth byte) is transferred, the MTCR of Channel 1 contains a 1 and the next

DMA request from the TLC is not allowed to reach the DMAC through onboard hardware.

Channel 1 is still active, waiting for another request, but never detects one. The PCL transition is

generated when the GPIB becomes synchronized.

Note: After a DMA transfer in which the carry cycle was used, Channel 1 must be stopped by

issuing a software abort command before another DMA transfer takes place. This is done

by writing to the CCR of Channel 1 with the SAB bit set.

In general, after a DMA transfer has completed with or without an error, the following actions

should be taken:

1. Read ISR2 to clear any interrupt bit set.

2. Read ISR1.

3. Clear IMR1.

4. Clear IMR2.

5. Write a value to CFG1 to unassert the PCL line of Channel 1. (A write to CFG1 clears the

circuitry on the board, which generates the GPIB handshake synchronization status signal.)

6. If a GPIB error occurred during the transfer (ERR bit set in the TLC's ISR1), poll the BTAC

and MTCR of the DMAC until you are satisfied that no DMA transfers are taking place (that

is, the transfer count is not changing). (This step is necessary because of a 68450 DMAC

bug that can cause the VMEbus to hang. If you do not wait for any pending DMA transfer

to complete before issuing a SAB, as called out in Step 7 below, the 68450 may incorrectly

remove its bus request before receiving a bus grant intended for it.)

7. Write a software abort to Channel 0.

8. Clear the Status Register of Channel 0.

9. Write a software abort to Channel 1 if a carry cycle was used.

10. Clear Status Register of Channel 1 to clear any remaining interrupt.

Terminating on END or EOS

The END RX bit in ISR1 is set when a GPIB END message is received. The END RX bit is also

set when an EOS message is received and the REOS bit of AUXR has been previously set.

(Receipt of the EOS message is determined by the contents of the DIR, the EOSR, and the value

of the BIN bit in the AUXRA.) The END RX bit in ISR1 may be polled during DMA transfers,

or, if the END IE bit in IMR1 and the EINT bit in CCR (Channel 1) are both set, a VMEbus

interrupt request (GPIB IR) occurs when END RX gets set.