Chapter 4 Register Bit Descriptions
© National Instruments Corporation 4-9 GPIB-1014 User Manual
Interrupt Status Register 1 (ISR1)VMEbus Address: Base Address + 113 (hex)
Attributes: Read Only, Internal to TLC
Bits are cleared when read
Interrupt Mask Register 1 (IMR1)VMEbus Address: Base Address + 113 (hex)
Attributes: Write Only, Internal to TLC
CPT
CPT IE APT
APT IE DET
DET IE END RX
END IE DEC
DEC IE ERR
ERR IE DO
DO IE DI
DI IE
R
W
7 654 3210
The Interrupt Status Register 1 (ISR1) is composed of eight Interrupt Status bits. The Interrupt
Mask Register 1 (IMR1) is composed of eight Interrupt Enable bits that directly correspond to
the Interrupt Status bits in ISR1. As a result, ISR1 and IMR1 service eight possible interrupt
conditions, where each condition has an Interrupt Status bit and an Interrupt Enable bit
associated with it. If the Interrupt Enable bit is true when the corresponding status condition or
event occurs, a hardware interrupt request is generated. Bits in ISR1 are set and cleared by the
TLC regardless of the status of the Interrupt bits in IMR1. If an interrupt condition occurs at the
same time ISR1 is being read, the TLC holds off setting the corresponding Status bit until the
read has finished.
Bit Mnemonic Description
7r CPT Command Pass Through Bit
7w CPT IE Command Pass Through Interrupt Enable Bit
CPT is set on:
[UCG + ACG & (TADS + LADS)] & undefined & ACDS & (CPT
ENABLE) + UDPCF & SCG & ACDS & CPT ENABLE
CPT is cleared by:
pon + (read ISR1)
Notes
UCG: GPIB Universal Command Group message
ACG: GPIB Addressed Command Group message
TADS: GPIB Talker Addressed State
LADS: GPIB Listener Addressed State
defined: GPIB command automatically recognized and
executed by TLC