National Instruments 320030-01

Chapter 6 Theory of Operation

Sources of errors are as follows:

• Configuration Error This occurs when any undefined or reserved bit pattern, or illegal

device/operand size combination is programmed into a channel and

an attempt is made to set the STR bit. This error occurs, for

example, when chaining is programmed and the continue bit is also

set, if the DTYP bit specifies a single-address transfer and the

device port size is not the same as the operand size, or if DTYP is

68000 or 6800 (DPS is 16 bits), SIZE is eight bits, and REQG is 10

bits or 11 bits (request pin). Setting an undefined configuration

signals a configuration error. The undefined configurations are :

XPM=01, MAC=11, DAC=11, CHN=01, SIZE=11. In any case,

the channel will not start.

• Operation Timing Error If a write access is attempted to certain registers or bits within

registers while a channel is active or if certain status bits are set, an

operation timing error occurs and the channel operation aborts if

the channel is active. This error will occur, for example, if an

attempt is made to continue an operation without STR being

simultaneously set, if the channel is not active, if an attempt to set

STR is made with ACT, COC, BTC, NPT, or ERR asserted, if an

attempt is made to write to the DCR, OCR, SCR, GCR, MAR,

DAR or MTCR with STR or ACT asserted, if an attempt to assert

CNT is made when CHN is 10 or 11, or if an attempt to assert

CNT is made when BTC and ACT are asserted.

• Address Error This is signaled if a word or longword operation is attempted to an

odd address.

• Bus Error This indicates a bus error occurred during the last bus cycle

generated by the channel.

• Count Error This is signaled if the MTCR or BTCR are initialized with terminal

count. A count error is signaled if a terminal count is encountered

during continue or chain processing.

• Abort This is signaled if the PCL was configured as an abort input and

made an active transition, or if the channel operation was aborted

by the SAB bit of the OCR. If the PCL is used as an abort input,

the PCT bit must be cleared prior to starting the channel.

The DMAC allows access to internal registers to implement error recovery procedures. If an

error occurs during a DMA transfer, appropriate information is available to the operating system

for a soft-failure operation. The operating system must be able to determine how much data was

transferred, where the data was transferred to, and what type of error occurred.

The information available to the operating system consists of the present values of the Memory

Address, Device Address and Base Address Registers, the Memory Transfer and Base Transfer

Counters, and the Control, Status, and Error Registers. After the successful completion of any