Theory of Operation Chapter 6
GPIB-1014 User Manual 6-8 © National Instruments Corporation
corresponds to the read access time of the TLC. Local signal SACK is asserted to drive VMEbus
signal DTACK* active to indicate that the data is valid on the VMEbus data lines D07 through
D00. The data remains valid and the DTACK* signal remains asserted until DS0* is released by
the bus master. When DS0* is released, the board first disables the data transceiver and then
releases DTACK*. At the same time, the circuitry delays for a recovery time of 250 nsec.
Signal END_RECOVERY is asserted at the end of the 250-nsec period to reset the Timing State
Machine. At this point the TLC can perform another read/write cycle.
During a write cycle to the TLC, CFG1, or CFG2, the timing is similar. Once DS0* is asserted,
the TLC signal WR* is driven low immediately. The WR* signal is ANDed with both CS1* and
CS2* to drive the clock inputs of the two Configuration Registers. Once WR* is driven low, the
circuitry counts a data setup time of 250 nsec. SACK then is asserted to drive the VMEbus
signal DTACK* low. At the same time, the WR* signal is immediately driven high to latch the
data into the TLC or the Configuration Registers. As soon as the master has released DS0*, the
board will release DTACK*. At the same time, the circuitry will start a recovery cycle of 250
nsec. Notice that recovery cycle is necessary to prevent another read or write cycle to the TLC.
DMA Cycles
The Timing State Machine also controls the timing of the TLC RD* and WR* signals during a
DMA operation. The sequence is similar to a normal TLC access, except that the 74S139
decoder is used to drive the TLC RD* and WR* signals as required to effect the DMA transfer.
The DMAC begins a DMA transfer for the TLC by driving either ACK0* or ACK1* low. The
Timing State Machine also starts when this is detected. When the transfer is from the TLC to the
VMEbus memory, the DMAC drives the VMEbus WRITE* line low, while the timing circuitry
drives the TLC RD* line low. The timing circuitry counts 250-nsec data access time and then
gates the DMAC data strobe signals UDS* and LDS* onto the VMEbus to drive the DS1* and
DS0* lines. The DMAC continues to drive the data strobes and the data lines with correct data
until the memory drives the DTACK* line. When DMAC has received DTACK* low, it first
releases its data strobes (UDS* and LDS*), then acknowledge lines (ACK0* or ACK1*). At this
time, the TLC RD* line is released. The timing circuitry then counts a recovery time of 250 nsec
while the DMAC and VMEbus memory finish the cycle.
When the DMA transfer is from VMEbus memory to the TLC, the sequence is similar. The
timing circuitry starts when ACK0* or ACK1* is detected low. The DMAC drives the VMEbus
data strobes as required and drives the VMEbus WRITE* line high, while the timing circuitry
drives the TLC WR* line low. Unlike the case when the board reads the TLC and writes to the
memory, data strobes from DMAC (UDS* and LDS*) are not held off. When the memory
responds with DTACK*, indicating that the data is valid on the bus, the DMAC waits a
minimum of 190 nsec then releases the data strobes. When the timing circuitry sees the data
strobes released, it immediately drives the TLC WR* line high, latching the data into the TLC.
When the DMAC has released ACK0* or ACK1*, the timing circuitry counts a recovery time of
250 nsec while the DMAC and memory finish the cycle. Notice the function of the flip-flop in
preventing another read/write cycle to the TLC during the recovery period. The flip-flop stays
set (Q=1) at all times before the recovery cycle, is cleared (Q=0) at the beginning of the recovery
cycle, and is set again at the end of the recovery period.