Chapter 2 General Description
© National Instruments Corporation 2-5 GPIB-1014 User Manual
Table 2-3. 68450 Internal DMA Registers (continued)
Address (Base
+ Hex Offset) Mode Register Channel Size
85 R/W Operation Control (OCR2) 2 8 bits
86 R/W Sequence Control (SCR2) 2 8 bits
87 R/W Channel Control (CCR2) 2 8 bits
AD R/W Channel Priority (CPR2) 2 8 bits
A5 R/W Normal Interrupt Vector (NIVR2) 2 8 bits
A7 R/W Error Interrupt Vector (EIVR2) 2 8 bits
CA R/W Memory Transfer Counter (MTCR3) 3 16 bits
CC R/W Memory Address Register (MAR3) 3 32 bits
E9 R/W Memory Function Code (MFCR3) 3 8 bits
D4 R/W Device Address Register (DAR3) 3 32 bits
F1 R/W Device Function Code (DFCR3) 3 8 bits
DA R/W Base Transfer Counter (BTCR3) 3 16 bits
DC R/W Base Address Register (BAR3) 3 32 bits
F9 R/W Base Function Code (BFCR3) 3 8 bits
C0 R/W Channel Status (CSR3) 3 8 bits
C1 R Channel Error (CER3) 3 8 bits
C4 R/W Device Control (DCR3) 3 8 bits
C5 R/W Operation Control (OCR3) 3 8 bits
C6 R/W Sequence Control (SCR3) 3 8 bits
C7 R/W Channel Control (CCR3) 3 8 bits
ED R/W Channel Priority (CPR3) 3 8 bits
E5 R/W Normal Interrupt Vector (NIVR3) 3 8 bits
E7 R/W Error Interrupt Vector (EIVR3) 3 8 bits
FF R/W General Control Register (GCR) all 8 bits
Table 2-4. GPIB-1014 Configuration Registers
Address
(Base + Hex Offset) Mode Register Size
101 W Configuration Register 1 8 bits
105 W Configuration Register 2 8 bits
VMEbus Master-Direct Memory Access
The GPIB-1014 can function as a VMEbus master, performing data transfers to and from
VMEbus memory. In most applications, the 68450 controls the data transfer to and from the
GPIB during DMA, and can transfer the 8-bit data on data lines D07 through D00 or D15
through D08, allowing the packing of data in VMEbus memory. In addition to GPIB-to-VMEbus
memory DMA transfers, the board can also perform 8- or 16-bit memory-to-memory DMA
transfers.