National Instruments 320030-01

Chapter 6 Theory of Operation

accepted the byte and the Talker may have already released DAV*. For this reason, the

synchronization circuitry looks at the level of the DAV* line rather than for a transition. When

the DAV* line is detected high, all devices have accepted the byte and a negative transition is

generated on the PCL of Channel 1, requesting an interrupt.

For the GPIB-1014 to wait until the GPIB is synchronized to signal that the DMA transfer is

complete, it must be configured to wait until the PCL transition occurs to notify the host CPU.

Each DMA channel of the DMAC has one interrupt enable, which generates an interrupt not only

for the PCL transition, but also if the COC bit is set in the channel CSR. The COC bit (Channel

Operation Complete) is set when the channel has finished its DMA transfer. If the channel was

operated in the chained mode (array or linked chained), COC will be set after the DMAC has

transferred the last data byte in the last data block of the chain. The condition of interest is not

just when the DMAC is finished, but when the DMAC is finished and the GPIB is synchronized

(that is, two conditions must be satisfied). Channel 1 is used to detect synchronization for both

carry cycle and non-carry cycle DMA transfers. Since non-carry cycle DMA transfers do not use

Channel 1, synchronization detecting on Channel 1 causes no conflict. Since carry cycle DMA

transfers briefly employ Channel 1, their operations require special considerations.

If the carry cycle feature is not enabled, Channel 0 transfers everything. It is desirable to disable

interrupts on Channel 0, but enable interrupts on Channel 1. A negative transition on the PCL of

Channel 1 occurs if the GPIB is synchronized requesting an interrupt (at this point Channel 0 is

already complete) . Since Channel 0 can terminate its operation normally, you can simply check

the COC and ERR bits in the CSR of Channel 0 to determine the success of the data transfer on

Channel 0.

If you do use the carry cycle feature, however, Channel 1 must not terminate its operation and set

the COC bit, as this termination will cause an interrupt immediately rather than waiting for the

GPIB to become synchronized. This is why Channel 1 is configured to operate in chained mode

with the length of the second (and also last) block in the chain set to two (one more byte than

needed). This value is loaded in the DMAC Channel 1 transfer count register. After one byte is

transferred (the last byte in the data buffer), DMA requests are automatically masked. Channel 1

is still active, expecting to transfer one more byte, but never sees another request, so the COC bit

is never set. The interrupt is disabled on Channel 0 but enabled on Channel 1. The GPIB

becoming synchronized, however, causes a negative transition on the PCL1, requesting an

interrupt. Before another DMA transfer with the carry cycle is attempted, Channel 1 must be

stopped by issuing a software abort by writing to the CCR with the SAB set.

After the last byte in a DMA transfer has been transferred to or from the TLC, writing any value

to CFG1 clears the circuitry, which detects GPIB synchronization. If GPIB synchronization has

already been detected, writing to CFG1 pulls the PCL high.

Regardless of whether the carry cycle feature was used, after a DMA transfer has completed, the

following actions must be taken in the order shown:

1. Read ISR2 (ISR2 must be read before reading ISR1).

2. Read ISR1.

3. Clear IMR1.