National Instruments 320030-01

Chapter 6 Theory of Operation

to service the request for the halted channel. When this bit is reset, the channel resumes

operation and services any request that may have been received while the channel was halted.

The HLT bit must be cleared to zero when writing to the STR bit to avoid immediate halt of the

channel.

Software Abort. The CCR has a software abort bit (SAB) that can abort the current operation of

the channel. Writing a 1 into the SAB causes a channel abort error to be signaled. The active

channel is then terminated immediately, the ACT bit is cleared, and both COC and ERR bits are

set. The abort status can be read in the Channel Error Register (CER). When the CCR is read,

the SAB always reads as a 0.

Interrupt Enable. The CCR has an interrupt enable bit (EINT) that the channel can use to request

interrupts on the completion of block transfers (bit BTC is set), on termination of channel

operations (bit COC is set), or on a negative transition on the PCL (bit PCT is set), if desired.

While the GPIB-1014 uses Channel 0 and 1, the interrupt is usually enabled in Channel 1 only

(see Chapter 5, Programming Considerations).

Block Termination

At the end of the transfer of an operand, the DMAC decrements the MTCR. If this counter is

decreased to the terminal count, the MTCR is exhausted and the operand is the last operand of

the block. The channel operation is complete if the operation is unchained and there is no

continuation, or if the operation is chained and the chain is exhausted (last block in the chain has

been transferred). When the last transfer of the last data block has been completed, the ACT bit

of the CSR is cleared and the COC bit is set, indicating the channel operation is complete.

A bus exception during a bus cycle being run for a channel or an error in the channel terminates

the block transfer and the channel operation. The bit of the CER corresponding to the error is

set. The ACT of the CSR is cleared and the COC and ERR bits are set.

Multiple Block Operations. When the MTCR is exhausted, there are additional blocks to be

transferred if the channel is chained and the chain is not exhausted. The DMAC provides the

re-initialization of the MAR and the MTCR.

Continued Operations. When the MTCR is exhausted and the continue bit of the CCR is set, the

DMAC performs a continuation of the channel operation.

1. First, the Base Address Register, the Base Function Code Register, and the Base Transfer

Count Registers are automatically copied into the Memory Address Registers, the Function

Code Registers, and Memory Transfer Count Registers.

2. The Block Transfer Complete (BTC) bit of the CSR is set.

3. The Continue bit is cleared.

4. The channel begins a new block transfer.