Index
© National Instruments Corporation Index-6 GPIB-1014 User Manual
DMA gating and control circuitry, 6-7 to 6-8
DMA registers
68450 internal DMA registers (chart), 2-5
Address Registers, 4-48
Base Address Register (BAR), 4-48
Base Transfer Counter Register (BTCR), 4-48
Channel Control Register (CCR), 4-56 to 4-57
Channel Error Register (CER), 4-60
Channel Priority Register (CPR), 4-61
Channel Status Register (CSR), 4-58 to 4-59
Configuration Register 1 (CFG1), 4-64 to 4-65
Configuration Register 2 (CFG2), 4-66 to 4-67
Device Address Register (DAR), 4-48
Device Control Register (DCR), 4-51 to 4-52
DMAC DMA channel register set (chart), 4-46
Function Code Registers, 4-50
General Control Register (GCR), 4-63
Interrupt Vector Registers, 4-62
Memory Address Register (MAR), 4-48
Memory Transfer Counter Register (MTCR), 4-48
Operation Control Register (OCR), 4-53 to 4-54
overview, 4-46 to 4-48
register map, 4-2
register memory map, 4-47
Sequence Control Register (SCR), 4-55
Transfer Count Registers, 4-48 to 4-49
DMAC (68450)
definition of, 2-12
initialization, 5-2
theory of operation, 6-14 to 6-22
DMAC channel operation
block termination
array chaining operations, 6-19 to 6-20
continued operations, 6-19
error conditions, 6-21 to 6-22
linked chaining operations, 6-20 to 6-21
multiple block operations, 6-19
overview, 6-19
initialization and transfer phases
address register operation, 6-17
address sequencing, 6-17
data transfers, 6-16
device port size, 6-17
device (TLC)/DMAC communication, 6-15
DMA requests, 6-16
operand size, 6-17
operands and addressing, 6-17
transfer count register operation, 6-17 to 6-18
initiation and control of channel operations