Programming Considerations Chapter 5
GPIB-1014 User Manual 5-12 © National Instruments Corporation
4. For array or linked chaining, load the MFCR of Channel 0 with the proper data to
generate the required Address Modifier Code to access the data blocks. See Tables
3-1 and 3-2 for recommended values.
5. Set up the data blocks and the address & transfer count array in VMEbus memory.
Figures 6-1 and 6-2 describe how to set up the array for both chaining modes.
Interrupts are generally not enabled for Channel 0. The CPR, NIVR, DAR, DFCR, and
EIVR of Channel 0 are generally not used.
3. Channel 1 must be programmed before starting the transfer in the following manner:
a. If VMEbus interrupts are used, complete the following events:
• Set the PCL bits in the DCR of Channel 1 to 01 for status input with interrupt.
• Set the EINT bit in the CCR of Channel 1 to enable interrupts.
• Load the NIVR and EIVR of Channel 1 with the proper status/ID byte to return to the
VMEbus interrupt handler.
b. If VMEbus interrupts are not used, complete the following event:
• Set the PCL bits in the DCR of Channel 1 to binary 00 for status input. You can
check the PCT and PCS bits in the CSR of Channel 1 to see if the TLC has requested
an interrupt, BERR* has occurred, or if GPIB synchronization has occurred.
It is not necessary to configure any other Channel 1 registers.
4. Once Channels 0 and 1 have been configured, the DMAC must be started by setting the STR
bit in the CCR of Channel 0. Channel 1 is not used.
5. Finally, configure the TLC for DMA operation by completing the following steps:
a. Set the END IE bit in IMR1 if the TLC is a GPIB Listener. Set the ERR IE bit in IMR1
if the TLC is a GPIB Talker. In all cases, clear all other IE bits.
b. Set the DMAO bit in IMR2 if the TLC is a GPIB Talker. Otherwise, clear DMAO.
c. Set the DMAI bit in IMR2 if the TLC is a GPIB Listener. Otherwise, clear DMAI.