Chapter 4 Register Descriptions
© National Instruments Corporation 4-43 GPIB-1014 User Manual
Address Register (ADR)VMEbus Address: Base Address + 11D (hex)
Attributes: Write Only, Internal to TLC
76543210
ARS DT DL AD5 AD4 AD3 AD2 AD1
W
The Address Register (ADR) is used to load the internal registers ADR0 and ADR1. Both
ADR0 and ADR1 must be loaded for all addressing modes.
Bit Mnemonic Description
7w ARS Address Register Select Bit
ARS is zero or one to select whether the seven low-order bits of ADR
must be loaded into internal registers ADR0 or ADR1, respectively.
6w DT Disable Talker Bit
DT must be set if recognition of the GPIB talk address formed from
AD5 through AD1 (ADR[4-0]w) is not to enable.
5w DL Disable Listener Bit
DL must be set if recognition of the GPIB listen address formed from
AD5 through AD1 (ADR[4-0]w) is not to enable.
4-0w AD[5-1] TLC GPIB Address Bits 5 through 1
These bits indicate the five low-order bits of the GPIB address that is
to be recognized by the TLC. The corresponding GPIB talk address is
formed by adding hex 40 to AD[5-1], while the corresponding GPIB
listen address is formed by adding hex 20. The value written to
AD[5-1] must not be all ones; otherwise, the corresponding talk and
listen addresses would conflict with the GPIB Untalk (UNT) and GPIB
Unlisten (UNL) commands.