Chapter 4 Register Descriptions
© National Instruments Corporation 4-35 GPIB-1014 User Manual
Parallel Poll Register (PPR)
VMEbus Address: Base Address + 11B (hex)
AUXMR Control Code: 011 (Binary, Bits 7 - 5)
Attributes: Write Only, Internal to TLC
Accessed through AUXMR
43210
W
U S P3 P2 P1
This 5-bit command code determines the manner in which the TLC responds to a Parallel Poll.
When using the remote Parallel Poll Configure (IEEE 488 capability code PP1), do not write to
the PPR. The TLC implements remote configuration fully and automatically without software
assistance. The hardware recognizes, interprets, and responds to Parallel Poll Configure (PPC),
Parallel Poll Enable (PPE), Parallel Poll Disable (PPD), and Identify (IDY) messages. It is only
necessary to set or clear the individual status (ist) message (using Set/Clear Parallel Poll Flag
auxiliary commands) according to pre-established system protocol convention. Writing to the
PPR after it is remotely configured will corrupt the configuration.
When using the local PPC (capability code PP2), a valid PPE or PPD message must be written to
the PPR prior to the poll.
Bit Mnemonic Description
4w U Unconfigure Bit
The U bit determines whether or not the TLC participates in a Parallel
Poll. If U=0, the TLC participates in Parallel Polls and responds in the
manner defined by PPR[3] through PPR[0] and by ist. If U=1, the
TLC does not participate in a Parallel Poll.
The U bit is equivalent to the Local Poll Enable, active low (lpe*)
message. When U=0, S and P[3-1] mean the same as the bit of the
same name in the PPE message, and the I/O write operation (to the
PPR) is the same as the receipt of the PPE message from the GPIB
Controller. When U=1, S and P[3-1] do not carry any meaning, but
they must be cleared.