General Description Chapter 2
GPIB-1014 User Manual 2-6 © National Instruments Corporation
Memory addresses generated by the GPIB-1014 are 24 bits wide and the VMEbus Address
Modifier Lines (AM5 through AM0) are fully programmable using function code registers
located in the 68450 and three hardware jumpers (W3, W4, and W5). (See Chapter 3 for
instructions on setting the hardware jumpers. See Chapter 4 for a description of the DMAC
Function Code Registers.) The 24-bit addresses, along with selectable Address Modifier codes,
eliminate artificial memory boundaries and allow data transfers between the GPIB and data area,
program area, or even devices located in the short I/O area. In VMEbus terminology, the
GPIB-1014 has A24 / D08(EO) & D16 master capability. The board does not use Unaligned
Transfer (UAT), Block Transfer (BLT), or Read Modify Write (RMW) cycles. The chaining
feature of the 68450 allows data blocks of unlimited size to be transferred.
Interrupter
Interrupt events that can drive a hardware-programmed VMEbus interrupt request line are as
follows:
• GPIB Data In (DI) • Address Status Change (ADSC)
• GPIB Data Out (DO) • Secondary Address Pass Through (APT)
• END Message Received (END RX) • Service Request Input (SRQI)
• GPIB Command Out (CO) • Device Execute Trigger (DET)
• Remote Mode Change (REMC) • Device Clear received (DEC RX)
• GPIB Handshake Error (ERR) • Command Pass Through (CPT)
• Lockout Change (LOKC) • Bus Error (BERR)
• GPIB DMA Transfer Finished and
GPIB Synchronized (FIN)
You can select one of seven VMEbus interrupt request lines (IRQ1* through IRQ7*) through
software using three bits located in Configuration Register 1.
The onboard hardware implements the VMEbus interrupt acknowledge protocol. Interrupt
Vector Registers located in the 68450 let you select, through software, the 8-bit Interrupt
Status/ID byte supplied by the GPIB-1014 during an interrupt acknowledge cycle of the correct
priority. The GPIB-1014 is a D08(O) interrupter, because it responds to an interrupt
acknowledge cycle by providing an 8-bit status/ID byte on data lines D00 through D07. In
addition, the board is a Release On Register Access (RORA) interrupter, because it releases its
interrupt line when the Channel Status Register is written with the proper value. In VMEbus
terminology, the GPIB-1014 has D08(O) / RORA Interrupter capability.