DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

2 FEATURE HIGHLIGHTS

2.1General

256-pin, 27mm BGA package

1.8V and 3.3V supplies

IEEE 1149.1 JTAG boundary scan

Software access to device ID and silicon revision

Development support includes evaluation kit, driver source code, and reference designs

Reference design routes on a two-layer PC board

Programmable output clocks for fractional T1, E1, H0, and H12 applications

2.2Microprocessor Interface

Parallel control port with 8-bit data bus

Nonmultiplexed Intel and Motorola timing modes

Internal software reset and external hardware reset-input pin

Supports polled or interrupt-driven environments

Software access to device ID and silicon revision

Global interrupt-output pin

2.3HDLC Ethernet Mapping

Dedicated HDLC controller engine for protocol encapsulation

Compatible with polled or interrupt driven environments

Programmable FCS insertion and extraction

Programmable FCS type

Supports FCS error insertion

Programmable packet size limits (Minimum 64 bytes and maximum 2016 bytes)

Supports bit stuffing/destuffing

Selectable packet scrambling/descrambling (X43+1)

Separate FCS errored packet and aborted packet counts

Programmable inter-frame fill for transmit HDLC

2.4X.86 (Link Access Protocol for SONET/SDH) Ethernet Mapping

Programmable X.86 address/control fields for transmit and receive

Programmable 2-byte protocol (SAPI) field for transmit and receive

32 bit FCS

Transmit transparency processing—7E is replaced by 7D, 5E

Transmit transparency processing—7D replaced by 7D, 5D

Receive rate adaptation (7D, DD) is deleted.

Receive transparency processing—7D, 5E is replaced by 7E

Receive transparency processing—7D, 5D is replaced by 7D

Receive abort sequence the LAPS packet is dropped if 7D7E is detect

Self-synchronizing X43+1 payload scrambling.

Frame indication due to bad address/control/SAPI, FCS error, abort sequence or frame size longer than preset max

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Maxim DS33R11 specifications General, Microprocessor Interface, Hdlc Ethernet Mapping