DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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(VDD = 3.3V ±5%, TA = -40°C to +85°C.) (Note 1, Figure 13-3, Figure 13-14, and Figure 13-15)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
488 (E1)
RDCLKO Period tLP 648 (T1)
ns
tLH (Note 2) 200 0.5 tLP
RDCLKO Pulse Width
tLL (Note 2) 200 0.5 tLP
ns
tLH (Note 3) 150 0.5 tLP
RDCLKO Pulse Width tLL (Note 3) 150 0.5 tLP ns
488 (E1)
RDCLKI Period tCP 648 (T1)
ns
tCH 20 0.5 tCP
RDCLKI Pulse Width tCL 20 0.5 tCP ns
(Note 4) 648
RSYSCLK Period tSP
(Note 5) 488 ns
tSH 20 0.5 tSP ns
RSYSCLK Pulse Width tSL 20 0.5 tSP ns
RSYNC Setup to RSYSCLK Falling tSU 20 ns
RSYNC Pulse Width tPW 50 ns
RPOSI/RNEGI Setup to RDCLKI Falling tSU 20 ns
RPOSI/RNEGI Hold from RDCLKI Falling tHD 20 ns
RSYSCLK, RDCLKI Rise and Fall Times tR, tF 22 ns
Delay RDCLKO to RPOSO, RNEGO
Valid tDD 50 ns
Delay RCLKO to RSERO, RDATA, RSIG
Valid tD1 50 ns
Delay RCLKO to RCHCLK, RSYNC,
RCHBLK, RFSYNC tD2 50 ns
Delay RSYSCLK to RSERO, RSIG Valid tD3 22 ns
Delay RSYSCLK to RCHCLK, RCHBLK,
RMSYNC, RSYNC tD4 22 ns
Note 1: Timing parameters in this table are guaranteed by design (GBD).
Note 2: Jitter attenuator enabled in the receive path.
Note 3: Jitter attenuator disabled or enabled in the transmit path.
Note 4: RSYSCLK = 1.544MHz.
Note 5: RSYSCLK = 2.048MHz.