DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

Register Name:

TR.T1RCR2

Register Description:

T1 Receive Control Register 2

Register Address:

04h

Bit #

Name

Default

7

6

5

4

3

2

1

0

RFM

RB8ZS

RSLC96

RZSE

RJC

RD4YM

0

0

0

0

0

0

0

0

Bit 6: Receive Frame Mode Select (RFM) 0 = D4 framing mode

1 = ESF framing mode

Bit 5: Receive B8ZS Enable (RB8ZS)

0 = B8ZS disabled

1 = B8ZS enabled

Bit 4: Receive SLC-96 Enable (RSLC96). Only set this bit to a 1 in D4/SLC-96 framing applications. See Section

10.18for details.

0= SLC-96 disabled

1= SLC-96 enabled

Bit 3: Receive FDL Zero-Destuffer Enable (RZSE). Set this bit to 0 if using the internal HDLC/BOC controller instead of the legacy support for the FDL. See Section 10.17 for details.

0 = zero destuffer disabled

1 = zero destuffer enabled

Bit 2: Reserved. Set to zero for proper operation.

Bit 1: Receive Japanese CRC6 Enable (RJC)

0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)

1 = use Japanese standard JT–G704 CRC6 calculation

Bit 0: Receive-Side D4 Yellow Alarm Select (RD4YM) 0 = 0s in bit 2 of all channels

1 = a 1 in the S-bit position of frame 12 (J1 Yellow Alarm Mode)

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Maxim DS33R11 TR.T1RCR2, RFM RB8ZS RSLC96 Rzse RJC RD4YM, Bit 6 Receive Frame Mode Select RFM 0 = D4 framing mode