Maxim DS33R11 Ethernet Mapper Clocks, Clocking Options for the Ethernet Interface, Txclk

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

9 ETHERNET MAPPER

9.1Ethernet Mapper Clocks

The DS33R11 clocks sources and functions are as follows:

•Serial Transmit Data (TCLKE) and Serial Receive Data (RCLKI) clock inputs are used to transfer data from the serial interface. These clocks can be continuous or gapped.

•System Clock (SYSCLKI) input. Used for internal operation. This clock input cannot be a gapped clock. A clock supply with ±100ppm frequency accuracy is suggested. A buffered version of this clock is provided on the SDCLKO pin for the operation of the SDRAM. A divided and buffered version of this clock is provided on REF_CLKO for the RMII/MII interface.

•Packet Interface Reference clock (REF_CLK) input that can be 25MHz or 50MHz. This clock is used as the timing reference for the RMII/MII interface.

•The Transmit and Receive clocks for the MII Interface (TX_CLK and RX_CLK). In DTE mode, these are input pins and accept clocks provided by an Ethernet PHY. In the DCE mode, these are output pins and will output an internally generated clock to the Ethernet PHY. The output clocks are generated by internal division of REF_CLK. In RMII mode, only the REF_CLK input is used.

•REF_CLKO is an output clock that is generated by dividing the 100MHz System clock (SYSCLKI) by 2 or 4.

•A Management Data Clock (MDC) output is derived from SYSCLKI and is used for information transfer between the internal Ethernet MAC and external PHY. The MDC clock frequency is 1.67MHz.

Clocking of the integrated T1/E1/J1 tansceiver is discussed in Section 10.1. The following table provides the different clocking options for the Ethernet interface.

Table 9-1. Clocking Options for the Ethernet Interface

RMIIMIIS	SPEED	DCE/ DTE	REF_CLKO	REF_CLK	RX_CLK
PIN			OUTPUT	INPUT
0 (MII)	10 Mbps	DTE	25MHz	25MHz	Input from
				±100ppm	PHY
0 (MII)	10 Mbps	DCE	25MHz	25MHz	2.5MHz
				±100ppm	(Output)
0 (MII)	100 Mbps	DCE	25MHz	25MHz	25MHz
				±100ppm	(Output)
1 (RMII)	10 Mbps	—	50MHz	50MHz	Not
				±100ppm	Applicable
1 (RMII)	100 Mbps	—	50MHz	50MHz	Not
				±100ppm	Applicable

TX_CLK

Input from

PHY

2.5MHz

(Output)

25MHz

(Output)

Not

Applicable

Not

Applicable

MDC

OUTPUT

1.67MHz

1.67MHz

1.67MHz

1.67MHz

1.67MHz

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